Standard Cell Layout With Grid Offsets for Routing Congestion

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Solution Overview

Problem

The reduction in device sizes in semiconductor processes leads to inefficiencies and increased number of standard cells in integrated circuits due to grid mismatch and routing congestion, which affects the performance and efficiency of integrated circuits.

Innovation Solution

The integrated circuit design includes standard cells with varying grid offsets and multi-patterning techniques to optimize layout, reducing grid mismatch and congestion by omitting certain patterns and employing multi-patterning to minimize collisions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If device sizes are reduced in semiconductor processes, then the number of devices in integrated circuit increases, but grid mismatch and routing congestion occur leading to reduced efficiency

Engineering Contradiction:

Improvenumber of devicesVSAvoidefficiency of integrated circuit

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments the integrated circuit layout into multiple standard cells, each with standardized dimensions and grid alignments. By dividing the circuit into modular standard cells with consistent grid structures, the patent eliminates grid mismatch between different device regions, enabling efficient routing while maintaining high device density.

Inventive Principle:

Principle #1Segmentation

2Productivity

If standard cells are arranged to comply with fabrication requirements, then the number of standard cells may be reduced, but area waste increases due to grid mismatch

Engineering Contradiction:

Improveefficiency of standard cellsVSAvoidarea waste

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by allowing different regions of the integrated circuit to have different grid offsets relative to a reference grid. Each standard cell is assigned a specific grid offset value that optimizes its layout for the local routing requirements, thereby minimizing area waste while maintaining compliance with fabrication process requirements.

Inventive Principle:

Principle #3Local quality

3Ease of operation

If multi-patterning techniques are employed to optimize layout, then routing congestion is reduced, but the complexity of the design process increases

Engineering Contradiction:

Improverouting congestionVSAvoiddesign process complexity

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by pre-defining multiple grid offset configurations for standard cells before the actual routing design. These pre-configured grid offsets are optimized to prevent routing congestion in advance, allowing designers to select appropriate configurations without dealing with complex routing adjustments during later design stages.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20260033010A1Integrated circuit including standard cells and method of designing the same

Publication Date: 2026.01.29 SAMSUNG ELECTRONICS CO LTD

AI summary

An integrated circuit may include a first function cell and a second function cell each corresponding to a first circuit, wherein the first function cell may include a first pattern extending in a first direction along a first grid in a first layer and a second pattern extending in the first direction along a second grid in a second layer, the first grid may have a first pitch greater than a second pitch of the second grid in a second direction crossing the first direction, and the second function cell may include a layout of the first function cell and have a length greater than a length of the first function cell by the first pitch in the second direction.