Standard Cell Height Non-Integer Metal Spacing

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Solution Overview

Problem

The existing methods for designing semiconductor device layouts manually or using semi-custom methods with standard cells face challenges in efficiently integrating complex circuit configurations, leading to unnecessary space due to standard cell heights being integer multiples of metal line spacings, resulting in inefficient use of area.

Innovation Solution

An electronic design automation method that generates standard cells and site-rows with a unit height as a non-integer multiple of metal line spacings, allowing metal routing tracks to start offset from the origin, thereby optimizing the layout to minimize area usage by aligning metal lines and standard cells efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the unit height of standard cells is designed as an integer multiple of metal line spacing according to standardized Floorplan rules, then the layout is easier to generate and metal routing is more standardized, but additional overhead space is introduced resulting in larger device area

Engineering Contradiction:

Improveease of layout generationVSAvoiddevice area

Core Design Contradiction:

Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent changes the parameter of standard cell height from being an integer multiple of metal line spacing to a non-integer multiple, specifically setting it to 0.8 times the metal line spacing. This parameter change eliminates the overhead space while maintaining ease of layout generation through automated design tools.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

Instead of making the standard cell height an integer multiple of metal line spacing (conventional approach), the patent inverts the relationship by making it a non-integer multiple (specifically 0.8x), thereby eliminating the overhead space that would otherwise be required.

Inventive Principle:

Principle #13The other way round (Inversion)

2Adaptability or versatility

If manual layout design methods are used for semiconductor devices with increasing integration and complex circuit configurations, then design flexibility is maintained, but design difficulty and time consumption increase significantly

Engineering Contradiction:

Improvedesign flexibilityVSAvoiddesign time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent establishes predetermined relationships between standard cell heights and metal line spacings (specifically the 0.8x ratio) before the actual layout design process. This preliminary standardization enables automated layout generation tools to efficiently handle complex circuit configurations without manual intervention, significantly reducing design time while maintaining flexibility.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10410917B2Semiconductor device including standard cell and electronic design automation method thereof

Publication Date: 2019.09.10 SAMSUNG ELECTRONICS CO LTD

AI summary

An electronic design automation method configured to automatically design a semiconductor device includes generating a site-row having a unit height based on a standard cell having the unit height, and generating metal routing tracks which begin at an offset point spaced a specific distance from an origin point of the site-row. The unit height is a non-integer multiple of a spacing of metal lines of one of interconnection layers of the semiconductor device. Using this process, a layout of a plurality of standard cells on a plurality of site-rows, and constituting a Floorplan of the semiconductor device, is generated.