Standard Cell Layout With Integrated TSVs for Backside Routing
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Solution Overview
Problem
Conventional standard cell designs are inefficient in using both frontside and backside of a wafer for signal routing, leading to area penalties and manufacturing challenges due to the separation of standard cells and through-silicon vias (TSVs), which complicates signal transition between the two sides.
Innovation Solution
Integration of TSVs into standard cells for enhanced backside signal routing, allowing for back-to-back, back-to-front, front-to-back, and front-to-front configurable standard cells, enabling efficient signal transition between frontside and backside routing layers and simplifying electronic design automation (EDA) support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional standard cells and TSV cells are separated to provide manufacturing clearance, then manufacturing is simplified, but area efficiency deteriorates due to increased footprint
Solution Approach 1:
The patent merges conventional standard cells and TSV cells into a single integrated standard cell structure. The TSVs are positioned within the standard cell boundaries, allowing both logic functionality and backside routing access to be achieved within the same cell footprint, thereby eliminating the need for separate TSV cells and reducing overall area while maintaining manufacturing clearance.
Solution Approach 2:
The patent utilizes the vertical dimension by integrating through-silicon vias that extend through the substrate thickness. This allows signal routing to access the backside of the wafer without increasing the lateral footprint of the standard cell, effectively using the third dimension (depth) to resolve the area efficiency problem.
2Device complexity
If only frontside signal lines are used for standard cell connection, then routing is simplified, but area efficiency deteriorates due to inability to utilize backside routing
Solution Approach 1:
The patent segments the routing function into frontside and backside components. Frontside signal lines handle local connections while TSVs provide access to backside routing layers for longer-distance or critical signal paths. This segmentation allows the design to utilize both sides of the wafer for routing, improving area efficiency without excessively increasing overall routing complexity.
Solution Approach 2:
The patent adds the backside routing dimension to the traditionally two-dimensional frontside routing plane. By incorporating TSVs that access backside metal layers, the design gains an additional routing dimension, allowing signals to be routed on the backside of the wafer and thereby improving area efficiency without proportionally increasing routing complexity.
3Adaptability or versatility
If TSVs are used to transition signals between backside and frontside, then backside routing is enabled, but area efficiency deteriorates due to increased cell separation requirements
Solution Approach 1:
The patent merges the TSV structure with the standard cell structure by positioning TSVs within the standard cell boundaries and integrating their routing paths. This integration eliminates the need for separate TSV cells and reduces the separation area between standard cells and TSV structures, thereby maintaining backside routing capability while improving area efficiency.
Data Source
AI summary
Various implementations described herein are directed to a device having a switch structure having an input and an output. The device may have a first thru-silicon via that couples a first backside signal to the input of the switch structure. The device may have a second thru-silicon via that couples a second backside signal to the output of the switch structure.