Standard Cell Layout Using Metal-1 Inter-Cell Routing to Cut IR Drop
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The metallization process in semiconductor devices faces challenges in scaling integrated circuits due to limitations in the routing capabilities of metal-1 layers, which are not bendable, leading to reduced density and increased IR drop when upper metal layers are used for interconnections.
Innovation Solution
Increasing the usage of metal-1 layers for inter cell routing and minimizing the use of upper metal layers, with metal-1 conduction paths extending across multiple cells and metal-2 paths perpendicular to metal-1 paths, to facilitate more flexible routing and reduce IR drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If upper metal layers are used for interconnections to overcome metal-1 routing limitations, then routing flexibility is improved, but density decreases and IR drop increases
Solution Approach 1:
The patent segments the routing function by dedicating specific metal-1 paths (first and second sets) exclusively for inter-cell routing, while other metal-1 paths serve intra-cell connections. This segmentation allows metal-1 to handle inter-cell routing without conflict, eliminating the need to use upper metal layers and thereby preventing IR drop while maintaining routing flexibility.
Solution Approach 2:
The patent introduces a dimensional organization by creating multiple horizontal direction conduction paths within the metal-1 layer itself, rather than moving to vertical upper metal layers. By establishing at least six horizontal conduction paths per cell in metal-1, the design achieves routing flexibility in the same layer, avoiding the penalties of using upper metal layers.
2Reliability
If metal-1 layers are used extensively for inter cell routing, then density is improved and IR drop is reduced, but routing flexibility is limited due to non-bendable metal-1 paths
Solution Approach 1:
The patent segments metal-1 conduction paths into different functional groups: first and second sets for inter-cell routing, and third and fourth sets for intra-cell connections. This segmentation allows each set to be optimized for its specific function, with inter-cell paths providing long horizontal connectivity without bends, achieving both reliability and flexibility.
Solution Approach 2:
The metal-1 layer is designed to perform multiple functions simultaneously: it provides both inter-cell routing (through first and second sets of horizontal paths) and intra-cell connections (through third and fourth sets). This multi-functionality eliminates the need to rely on upper metal layers, maintaining density and reducing IR drop while still providing routing flexibility.
3Ease of manufacture
If standard cell layout uses limited metal-1 paths for interconnections, then manufacturing is simplified, but routing capabilities are insufficient for dense integration
Solution Approach 1:
The patent segments metal-1 conduction paths into distinct sets with specific routing functions. The first and second sets provide dedicated inter-cell routing paths, while the third and fourth sets handle intra-cell connections. This segmentation maintains manufacturing simplicity by using standard metal-1 deposition processes while dramatically improving routing capability through systematic path organization.
Solution Approach 2:
The patent changes the parameter of metal-1 layer configuration by establishing at least six horizontal direction conduction paths per cell, with specific sets dedicated to inter-cell routing. This parameter change transforms metal-1 from a limited interconnection resource into a capable routing layer that can handle dense integration requirements without complicating the manufacturing process.
Data Source
AI summary
A method of fabricating an integrated circuit is disclosed. The method comprises defining a multi-layer semiconductor device structure on a substrate using standard cells, defining an input port on the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer, and defining a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths. The method further comprises defining a metal-2 layer over the metal-1 layer and configuring the first set of metal-1 conduction paths and the metal-2 conduction paths to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths.