Standard Cell Placement for IR Drop and Timing Balance
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Solution Overview
Problem
Conventional solutions for mitigating IR drop in integrated circuits, such as cell downsizing and adding power staples, fail to address the robust constraint-based mathematical representation of operating behavior, leading to timing pushout and IR drop vulnerability in other areas.
Innovation Solution
The method involves reorganizing standard cell placement within bounding box regions of an integrated circuit to normalize power density across supply rails, distributing current consumption more evenly and reducing current spikes, without the need for cell downsizing or buffering areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cell downsizing is used to mitigate IR drop, then IR drop is reduced in some areas, but timing pushout occurs in other areas
Solution Approach 1:
The patent applies local quality by making the placement density adjustable at different locations within the bounding box region. High-density placement is applied in areas where IR drop mitigation is needed, while low-density placement is applied in areas where timing is critical, thus resolving the contradiction between IR drop mitigation and timing performance
Solution Approach 2:
The patent introduces dynamic placement density that can be adjusted based on local conditions within the bounding box region. The placement density is not fixed but can be varied to optimize both IR drop mitigation and timing performance in different areas simultaneously
2Reliability
If buffering areas are required around high switching activity cells, then IR drop is mitigated in those areas, but device area increases
Solution Approach 1:
The patent merges the IR drop mitigation function with the standard cell placement structure by using placement density control within the bounding box region. Instead of adding separate buffering areas, the mitigation is achieved through optimized cell distribution, thus eliminating the need for additional buffering area
Solution Approach 2:
The patent extracts the buffering function from the traditional separate buffering area structure and integrates it into the cell placement density control mechanism within the bounding box region, thereby eliminating the need for dedicated buffering areas while maintaining IR drop mitigation
3Ease of manufacture
If conventional placement techniques are used, then placement is simple, but IR drop vulnerability and timing pushout occur
Solution Approach 1:
The patent changes the placement density parameter within the bounding box region to optimize both IR drop mitigation and timing performance. By controlling the placement density parameter, the system achieves reliable IR drop mitigation while maintaining placement simplicity through automated control
Data Source
AI summary
To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.