Standard Cell Leakage Characterization via Dummy Gate Isolation
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Solution Overview
Problem
Conventional standard cell architectures with continuous oxide definition (OD) regions face challenges in accurately characterizing leakage current due to uncertainties in whether a diffusion region acts as a source or drain, complicating performance prediction and design optimization in deep sub-micron process nodes.
Innovation Solution
A novel cell architecture where the drain is defined in a portion of the OD region stretching from the gate to a first side of an adjacent dummy gate, with a local interconnect structure coupling the drain-side dummy gate and the OD region adjacent its opposing side to a source voltage, ensuring consistent leakage current characterization regardless of adjacent cell configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If continuous OD region is used to achieve adequate lattice strain, then transistor strength is improved, but leakage current characterization becomes uncertain and complicated
Solution Approach 1:
The continuous OD region is segmented into discrete cell units, each with defined boundaries. Each cell contains a transistor with source and drain regions, and dummy gates that electrically isolate adjacent cells. This segmentation allows leakage current to be characterized at the cell level while maintaining continuous OD for strain engineering across multiple cells.
Solution Approach 2:
Dummy gates serve as intermediary structures between adjacent transistors in the continuous OD region. These dummy gates are electrically isolated and tied to appropriate voltages (VDD for PMOS, ground for NMOS), acting as mediators that prevent direct electrical interaction between adjacent active transistors while maintaining the continuous strained OD region.
2Strength
If OD regions are extended to form continuous OD, then transistor strength increases, but drain-to-source shorting risk increases
Solution Approach 1:
Dummy gates act as intermediary isolation structures between adjacent transistor drain and source regions in the continuous OD layout. By being electrically isolated and properly biased, they prevent direct drain-to-source shorting while allowing the OD region to remain continuous for strain purposes.
Solution Approach 2:
Dummy gates are tied to equipotential voltages matching their adjacent source regions (VDD for PMOS sources, ground for NMOS sources). This equipotential configuration ensures no voltage-driven current flow occurs through dummy gates, effectively preventing shorting while maintaining structural continuity.
3Reliability
If dummy gates are used to isolate transistors in continuous OD, then transistor isolation is achieved, but standard cell leakage calculation becomes complex
Solution Approach 1:
The continuous OD structure is divided into standardized cell units with clear boundaries defined by dummy gates. Each cell can be independently characterized for leakage current, and total leakage is calculated by summing contributions from individual cells. This segmentation transforms a complex continuous system into manageable discrete units.
Solution Approach 2:
The leakage current model changes from a continuous complex calculation to a discrete summation of standardized cell parameters. Each cell's leakage is characterized under defined conditions (with dummy gates properly biased), and total leakage is obtained by multiplying cell leakage by the number of cells, significantly simplifying the calculation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides predictable and consistent leakage current characterization, simplifying circuit design and analysis by eliminating uncertainties related to source-to-source or source-to-drain abutments, allowing for reliable leakage current calculation based on the number of cells.
Implementation Method 1
a local interconnect structure coupling the drain-side dummy gate and the OD region adjacent its opposing side to a source voltage
Data Source
Figure 1~2
Figure 3
Figure 4A
AI summary
A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage.