Standard Cell Library Third Power Rail Routing

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Solution Overview

Problem

As integrated circuit sizes increase, reducing transistor size uniformly to minimize cell size becomes challenging, leading to increased complexity in the lowest metal layer and reduced effective cell size, making it difficult to implement desired functions.

Innovation Solution

A standard cell library design that includes a first power rail, a second power rail, and a third power rail, with standard cells of different heights, where the first standard cell is electrically connected to the third power rail and uses the lowest metal layer for signal routing, while the third power rail is partially in a higher metal layer, allowing for enhanced routability and implementation of complex functions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If sizes of all transistors of the cell are uniformly reduced, then cell size is reduced, but implementation of desired function becomes more difficult and complexity of the lowest metal layer increases

Engineering Contradiction:
Improvecell sizeVSAvoidcomplexity of the lowest metal layer
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The patent introduces a third power rail positioned between the first and second power rails, creating an additional spatial dimension for power distribution. This allows standard cells to be arranged in multiple rows (first row between first and third power rails, second row between third and second power rails), thereby utilizing vertical layering to reduce routing complexity in the lowest metal layer while maintaining compact cell sizes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The power distribution network is segmented into multiple independent power rails (first, second, and third power rails) that can serve different standard cell rows. This segmentation allows independent routing and power management for different cell rows, reducing the complexity of the lowest metal layer by distributing power delivery across multiple separated pathways rather than a single congested layer

Inventive Principle:
Principle #1Segmentation

2Volume of moving object

If sizes of all transistors of the cell are uniformly reduced, then cell size is reduced, but it becomes more difficult to implement a desired function

Engineering Contradiction:
Improvecell sizeVSAvoidimplementation of desired function
Core Design Contradiction:
Volume of moving objectVSAdaptability or versatility

Solution Approach 1:

By adding the third power rail and organizing standard cells into multiple rows, the patent creates additional routing dimensions and pathways. This multi-row configuration provides more flexibility for implementing complex logic functions and desired circuit behaviors, as signals can be routed through different rows and power distributions can be optimized for specific cell types, thereby maintaining functional adaptability despite reduced transistor sizes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If conventional standard cell uses only the lowest metal layer, then routing is simplified, but effective cell size increases rather than decrease

Engineering Contradiction:
Improverouting complexityVSAvoideffective cell size
Core Design Contradiction:
Device complexityVSVolume of moving object

Solution Approach 1:

The patent utilizes multiple metal layers (first metal layer for first row standard cells, second metal layer for second row standard cells) to provide vertical routing separation. This allows signals from different cell rows to be routed in different metal layers, reducing horizontal routing congestion and enabling more compact cell layouts. The third power rail can be implemented in higher metal layers, freeing up the lowest metal layer for signal routing while maintaining efficient power distribution

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8174052B2Standard cell libraries and integrated circuit including standard cells
Publication Date: 2012.05.08 SAMSUNG ELECTRONICS CO LTD
  • US8174052B2 patent drawing
  • US8174052B2 patent drawing
  • US8174052B2 patent drawing

AI summary

A standard cell library includes a first power rail, a second power rail, a third power rail, a first standard cell, and second standard cells. The first power rail extends in a first direction. The second power rail extends in the first direction, and is spaced apart from the first power rail by a predetermined spacing in a second direction perpendicular to the first direction. The third power rail extends in the first direction between the first power rail and the second power rail. The first standard cell has at least one cell having a first cell height, and is arranged between the first power rail and the second power rail. The second standard cells have at least two cells, each having a second cell height, that are in contact with each other in the second direction, and are in contact with the first standard cell in the first direction.