Standard Cell Library Via Placement Optimization

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Solution Overview

Problem

The complexity of semiconductor manufacturing processes, particularly due to reduced transistor sizes, leads to increased defects and performance deterioration in semiconductor devices, necessitating improved methods for reducing defective device frequency and enhancing IC performance.

Innovation Solution

A standard cell library is developed, including information on standard cells with specific pin regions and marker information, allowing for optimal via placement to minimize resistance and improve timing characteristics, thereby enhancing IC performance and yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If transistor sizes are reduced to increase integration density, then more transistors can be integrated into a single chip, but manufacturing complexity increases and defect frequency increases

Engineering Contradiction:

Improvenumber of transistors per chipVSAvoiddefect frequency

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The pin is divided into first and second regions with different via placement characteristics. The second region is specifically designed to provide lower via resistance, creating local quality differentiation within the pin structure to optimize electrical performance while maintaining manufacturing feasibility

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The invention changes the spatial parameter of via placement by introducing marker information that specifies different regions within the pin. This parameter change allows optimization of via resistance without changing the overall pin structure or requiring additional manufacturing steps

Inventive Principle:

Principle #35Parameter changes

2Quantity of substance

If transistor sizes are reduced to increase integration density, then more transistors can be integrated into a single chip, but process complexity increases leading to performance deterioration

Engineering Contradiction:

Improvenumber of transistors per chipVSAvoidperformance characteristics

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

Marker information is prepared in advance during standard cell library creation, specifying optimal via placement regions before actual IC manufacturing. This preliminary action guides subsequent manufacturing processes to achieve better performance without increasing process complexity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The marker information acts as an intermediary between the standard cell design and the actual via placement process. It translates design requirements into specific manufacturing guidance, bridging the gap between design intent and manufacturing execution

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of manufacture

If via is placed in the first region of the pin, then via placement is straightforward, but resistance value is higher causing increased signal delay

Engineering Contradiction:

Improvevia placement simplicityVSAvoidsignal delay

Core Design Contradiction:

Ease of manufactureVSLoss of time

Solution Approach 1:

The pin is segmented into regions with different electrical characteristics. The second region is specifically engineered to provide lower via resistance, creating local quality differentiation that optimizes signal transmission speed without complicating the overall manufacturing process

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The invention replaces complex via placement decision-making with a simplified marker-based system. Instead of requiring complex analysis during manufacturing, pre-defined marker information directly indicates optimal via locations, substituting computational complexity with straightforward pattern recognition

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9852252B2Standard cell library and methods of using the same

Publication Date: 2017.12.26 SAMSUNG ELECTRONICS CO LTD

AI summary

A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.