Standard Cell Manufacturability via Lithography Hot Spot Detection
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Solution Overview
Problem
Conventional standard cell physical implementation processes fail to predict and prevent lithography hot spots after physical implementation, requiring significant time and effort to resolve issues that affect the yield of integrated circuits.
Innovation Solution
A method and system that generate random contexts for standard cells, insert vias based on design rules, and perform lithography verification to detect and address potential hot spots early in the design process, optimizing manufacturability by marking pin connections and applying via insertion rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If physical implementation is performed without prior lithography verification, then standard cells can be implemented using conventional routing tools, but lithography hot spots are not detected until after implementation, requiring significant time and effort to resolve
Solution Approach 1:
The patent applies preliminary action by performing lithography verification simulation during the standard cell design phase, before physical implementation. The system generates random contexts, inserts vias, and executes lithography verification to detect hot spots in advance, allowing engineers to resolve issues before tape-out, thereby eliminating post-implementation debugging time
Solution Approach 2:
The patent uses copying by creating simulated contexts that replicate real-world manufacturing conditions. The system generates random wire patterns and via configurations that mirror actual physical implementations, allowing hot spots to be detected in the simulation environment before committing to physical manufacturing
2Reliability
If random contexts are generated and lithography verification is performed early in the design process, then hot spots can be detected and resolved before physical implementation, but additional processing steps are required
Solution Approach 1:
The patent applies self-service by implementing automated via insertion and lithography verification processes that operate without manual intervention. The system automatically generates random contexts, inserts vias according to design rules, performs lithography verification, and identifies hot spots, reducing the need for manual layout engineering effort
Solution Approach 2:
The patent applies universality by creating a multi-functional system that combines context generation, via insertion, and lithography verification into a single integrated process. The via insertion deck module serves multiple purposes: generating via patterns, applying design rules, and preparing data for lithography verification, thereby managing complexity through functional integration
Data Source
AI summary
A method for optimizing manufacturability of standard cells includes generating random contexts for the standard cells, inserting vias into the standard cells, and performing a lithography verification on the standard cells after the vias have been inserted. The method enables early detection and resolution of potential hot spots on standard cell pin connections and reduction of hot spots that are introduced by the router at the chip level. The early detection and reduction of hot spots shortens the cycle time of a standard-cell based design.