Standard Cell Circuit Layout for Low-Track Nanosheet FETs
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Solution Overview
Problem
The reduction of track height in semiconductor devices leads to reduced PN separation between transistors, complicating gate formation and potentially reducing drive current, especially in nanosheet-based FETs.
Innovation Solution
A circuit cell design featuring two FET devices with offset gate and source/drain body portions arranged on opposite sides of a shared routing track, allowing for thinner or omitted gate spacers and independent gate formation, which mitigates the PN separation challenge and enables a low track height without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If track height is reduced to improve area efficiency, then area efficiency is improved, but PN separation between transistors is reduced
Solution Approach 1:
The patent transitions from a conventional planar arrangement where gate and source/drain bodies are aligned in the same track to a three-dimensional offset arrangement. The gate body is positioned in a first track while the source/drain bodies are positioned in a second track, creating vertical separation in the track dimension. This dimensional change allows reduced track height while maintaining adequate PN separation through the offset positioning.
Solution Approach 2:
The patent segments the gate body and source/drain bodies into separate spatial locations along different routing tracks. Instead of having all components in a single aligned structure, the gate body portion and source/drain body portions are divided and placed in different tracks, enabling independent optimization of track height and PN separation.
2Area of stationary object
If track height is reduced to improve area efficiency, then area efficiency is improved, but gate formation becomes more difficult
Solution Approach 1:
By moving the gate body to a different track level than the source/drain bodies, the patent creates additional vertical space that simplifies gate formation processes. The offset arrangement provides better access and separation for deposition and patterning operations, making gate formation easier even with reduced overall track height.
Solution Approach 2:
The patent introduces routing tracks as intermediary layers that separate and organize the gate body and source/drain bodies. These tracks act as mediators that provide spatial separation and facilitate independent formation processes, allowing gate and source/drain structures to be manufactured with greater ease and precision.
3Length of stationary object
If channel width is reduced to increase PN separation, then PN separation is improved, but drive current is reduced
Solution Approach 1:
Instead of reducing channel width to increase PN separation, the patent uses track offset to achieve separation in the vertical dimension. The channel width can be maintained at optimal levels for drive current performance while PN separation is achieved through the vertical displacement of gate and source/drain bodies onto different tracks.
Solution Approach 2:
The patent changes the spatial arrangement parameter from horizontal alignment to vertical offset between tracks. This parameter change allows PN separation to be achieved through track-level displacement rather than channel width reduction, thereby preserving drive current performance while achieving the required separation.
Data Source
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AI summary
The disclosure relates to a circuit cell for a standard cell semiconductor device, comprising: a first and second FET device, each comprising: a source body and a drain body, each comprising a common source or drain body portion and a set of source or drain prongs protruding from the common source or drain body portion, a set of channel layers, each channel layer extending between a pair of source and drain prongs, and a gate body comprising a common gate body portion and a set of gate prongs protruding from the common gate body portion. The common source and drain body portions of the first FET device are arranged along a first routing track. The common source and drain body portions of the second FET device are arranged along a third routing track. The channel layers of the first and second FET devices are arranged along a second routing track intermediate the first and third routing tracks. The source and drain prongs of the first FET device and the second FET device protrude from the respective common source or drain body portions to define an overlap with the second routing track. The common gate body portion of the first and second FET devices are arranged along the third and first routing track, respectively. The gate prongs of the first and the second FET device protrude from the respective common gate body portions to define an overlap with the second routing track.