Standard Cell Sign-Off Using Marker Layers for Connection Reliability
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Solution Overview
Problem
In semiconductor IC design, standard cells often have non-ideal pin connection patterns that are not detected by IC design tools, leading to potential malfunction or device failure due to increased contact resistance and decreased current driving capability in high-driving standard cells.
Innovation Solution
A 'sign-off' method using marker layers is implemented to detect and restrict unacceptable connection patterns in standard cells, ensuring proper electromagnetic circuit performance by marking must-join pins and groups, which are then checked against design criteria during the GDS sign-off process to prevent unacceptable connection patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard cell pin connections are not strictly checked during design, then design flexibility and tool simplicity are maintained, but connection reliability and device performance deteriorate due to non-ideal connection patterns
Solution Approach 1:
The patent applies preliminary action by pre-defining acceptable connection patterns and must-join pin groups before the actual connection process. The design tool automatically checks connections against these pre-established criteria, ensuring reliability without adding complex manual verification steps during the design process.
Solution Approach 2:
The patent changes the parameter of connection verification from manual inspection to automated pattern matching. By transforming the verification process into a parameter-based automated check against predefined acceptable patterns, the system improves reliability while maintaining design tool simplicity.
2Reliability
If marker layers are added to standard cells for connection pattern detection, then connection reliability improves through automated checking, but manufacturing complexity increases due to additional GDS file processing steps
Solution Approach 1:
The marker layer serves multiple functions: it identifies must-join pins, defines acceptable connection patterns, and enables automated verification. This multi-functionality reduces the need for separate verification mechanisms, ultimately simplifying the overall manufacturing process despite the added layer.
Solution Approach 2:
The design file itself contains the verification criteria through marker layers and acceptable connection pattern definitions. The system performs self-verification by automatically checking connections against these embedded criteria, eliminating the need for external manual verification processes.
3Measurement precision
If automated connection pattern checking is implemented, then detection precision of unacceptable patterns improves, but processing time increases due to additional verification steps
Solution Approach 1:
By pre-defining acceptable connection patterns and must-join pin groups before the connection process, the system enables rapid automated verification. The preliminary setup creates a reference framework that allows quick comparison during checking, improving detection precision without significant time penalty.
Solution Approach 2:
The patent uses pattern copying by storing acceptable connection patterns as reusable templates. During verification, the system copies and compares these predefined patterns against actual connections, enabling fast and precise detection without complex real-time analysis.
Data Source
AI summary
The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.