Standard-Cell Layout With MEOL Paths for Lower Parasitic Resistance
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Solution Overview
Problem
In emerging technology nodes, the small size of transistor components leads to restrictive topology choices for routing back-end-of-the-line (BEOL) metal interconnect layers, resulting in significant parasitic resistance that degrades transistor device performance.
Innovation Solution
The integration of parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which increases the cross-sectional area for current flow, thereby reducing parasitic resistance and capacitance in the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor components are reduced in size to increase device density, then the number of devices per chip increases, but parasitic resistance in the interconnect layers increases significantly
Solution Approach 1:
The patent introduces a middle-end-of-line (MEOL) interconnect layer positioned vertically between the front-end-of-line (FEOL) transistor layer and the back-end-of-line (BEOL) interconnect layers. This adds a new dimensional layer to the interconnect architecture, creating additional conductive pathways that reduce parasitic resistance without increasing lateral footprint, thereby maintaining high device density while mitigating the harmful effect of parasitic resistance.
Solution Approach 2:
The MEOL interconnect layer acts as an intermediary structure that bridges the FEOL and BEOL layers. It provides intermediate connection points and alternative current paths, mediating the electrical connection between transistors and upper interconnect layers. This intermediary layer reduces the direct current path length and resistance between FEOL devices and BEOL routing, effectively lowering parasitic resistance while preserving the compact high-density layout.
2Device complexity
If conventional single-path interconnect routing is used, then layout simplicity is maintained, but parasitic resistance and capacitance increase
Solution Approach 1:
The patent segments the interconnect routing into multiple independent layers: FEOL, MEOL, and BEOL. Each layer handles specific routing functions, with the MEOL layer providing intermediate segmentation of current paths. This segmentation creates multiple parallel conductive pathways, reducing parasitic resistance and capacitance by distributing current flow across separate routes rather than relying on a single congested path.
Solution Approach 2:
By adding the MEOL layer in the vertical dimension, the patent transforms the traditional planar two-layer interconnect structure into a three-layer vertical stack. This dimensional expansion provides additional routing resources without complicating the lateral layout, allowing current to flow through multiple vertical and horizontal paths that reduce parasitic effects while maintaining routing simplicity.
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.