Standard Cell Layout Using Metal-1 Routing Across Multiple Cells
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Solution Overview
Problem
The metallization process in semiconductor devices faces challenges in scaling integrated circuits due to limitations in metal-1 routing, which restricts the placement of standard cells and increases IR drop and routing complexity.
Innovation Solution
Increasing the usage of metal-1 for inter-cell routing and reducing upper level metal usage by configuring metal-1 and metal-2 layers with perpendicular conduction paths, allowing metal-1 paths to span across multiple cells and minimizing the use of higher metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If metal-1 routing is used for inter-cell connections, then routing flexibility is improved, but standard cell placement is restricted and routing complexity increases
Solution Approach 1:
The patent introduces a two-set conduction path system in the metal-1 layer (first set and second set of conduction paths) that operate in different directional dimensions. The first set extends across multiple cells while the second set remains confined within cells, creating a multi-dimensional routing architecture that resolves the conflict between routing flexibility and placement restrictions.
2Adaptability or versatility
If upper level metal layers are used for inter-cell routing, then standard cell placement flexibility is improved, but IR drop increases
Solution Approach 1:
Instead of using upper metal layers (metal-2, metal-3, etc.) for inter-cell routing as is conventional, the patent inverts the approach by making metal-1 the primary inter-cell routing layer. The first set of metal-1 conduction paths is specifically configured to extend across multiple cells, reversing the typical hierarchy and reducing the number of vias required, thereby minimizing IR drop.
3Productivity
If metal-1 conduction paths are configured to extend across multiple cells, then inter-cell routing efficiency is improved, but intra-cell routing options are reduced
Solution Approach 1:
The patent segments the metal-1 conduction paths into two distinct sets: a first set that extends across multiple cells for efficient inter-cell routing, and a second set that remains confined within individual cells for flexible intra-cell routing. This segmentation allows each set to be optimized for its specific function without compromising the other.
Solution Approach 2:
The metal-1 layer is given multi-functional capability by incorporating both first set and second set of conduction paths. This allows the metal-1 layer to simultaneously serve as an inter-cell routing layer (first set) and an intra-cell routing layer (second set), eliminating the need for separate routing layers for different functions.
Data Source
AI summary
A method of fabricating an integrated circuit is disclosed. The method comprises defining a multi-layer semiconductor device structure on a substrate using standard cells, defining an input port on the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer, and defining a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths. The method further comprises defining a metal-2 layer over the metal-1 layer and configuring the first set of metal-1 conduction paths and the metal-2 conduction paths to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths.