Standard Cell Fin Structure With Filler Cells for Mixed Fin Widths
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Solution Overview
Problem
Existing methods for integrating standard cells of varying sizes and structures in integrated circuits are not entirely satisfactory, particularly in achieving specific target performance at reduced length scales, such as varying fin widths across different standard cells, which affects design flexibility and performance.
Innovation Solution
The semiconductor structure includes fin active regions with varying widths across standard cells, with filler cells used to accommodate these variations, and a method involving selective epitaxial growth and patterning of fin structures, along with the use of metal and dielectric gate stacks to form functional and dummy gate structures, allowing for continuous fin extensions between standard cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard cells of various sizes and structures are integrated to provide design flexibility and achieve specific target performance, then design flexibility and performance are improved, but manufacturing complexity and layout difficulty increase
Solution Approach 1:
The standard cell layout is segmented into multiple lanes (first lane, second lane, third lane) with standardized pitch relationships. Each lane contains fin structures that can be independently configured with different widths, allowing variation in device characteristics while maintaining overall layout regularity through the segmented lane structure.
Solution Approach 2:
Different fin structures within the same standard cell are assigned different widths to achieve local optimization of device performance. The first fin structure has a first width, the second fin structure has a second width, and the third fin structure has a third width, allowing each region to be optimized for its specific functional requirement while maintaining standardized cell boundaries.
2Reliability
If fin widths are varied across different standard cells to achieve specific performance targets, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
Mandrel structures are formed first as templates before the fin structures are created. The mandrels define the precise locations and widths of subsequent fin structures through a controlled process sequence. This preliminary patterning step ensures that fins with different widths are formed with high precision by transferring the mandrel pattern through epitaxial growth and etching processes.
Solution Approach 2:
The fin width parameter is systematically varied across different fin structures (first width, second width, third width) to achieve different device characteristics. By controlling the mandrel dimensions and using selective epitaxial growth, precise fin width parameters are achieved while maintaining manufacturing control through standardized process parameters.
3Adaptability or versatility
If continuous fin extensions are implemented between standard cells, then design flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The fin structures serve multiple functions: they form active devices within standard cells, provide continuous extensions between cells for interconnect purposes, and maintain standardized pitch relationships for routing. This multi-functionality is achieved by forming fins that span cell boundaries while maintaining consistent width relationships, allowing the same fin structure to serve both device and interconnect functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances design flexibility and performance by enabling the integration of standard cells with different fin widths, improving current output for high-speed applications and reducing power consumption, while maintaining layout symmetry and balance in device performance.
Implementation Method 1
a method involving selective epitaxial growth and patterning of fin structures
Data Source
AI summary
An integrated circuit (IC) structure includes a fin structure protruding from a semiconductor substrate, the fin structure including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction. The IC structure also includes a first standard cell including a first metal gate stack engaged with the first portion, a second standard cell including a second metal gate stack engaged with the second portion, and a filler cell disposed between the first standard cell and the second standard cell, where the filler cell includes the third portion that connects the first portion to the second portion. The IC further includes a dielectric gate defining a first boundary of the filler cell and a third metal gate stack defining a second boundary of the filler cell, where the dielectric gate and the third metal gate stack are separated by a one-pitch spacing.