Standard Cell Layout With Non-Integral Pitch for Smaller IC Die

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Solution Overview

Problem

Existing integrated circuit design methods require standard cells to have cell heights that are integral multiples of the nominal minimum pitch, limiting design flexibility and potentially increasing the overall die size of the integrated circuit.

Innovation Solution

The design allows standard cells to have cell heights that are non-integral multiples of the nominal minimum pitch, providing more flexibility in design without necessitating enlargement of the standard cell size, and utilizing virtual grid lines for routing to optimize the integrated circuit layout.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If standard cells are designed with cell heights that are integral multiples of the nominal minimum pitch, then manufacturing compliance is ensured, but design flexibility is limited and die size increases

Engineering Contradiction:
Improvedesign flexibilityVSAvoiddie size
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent segments the rigid constraint of integral multiple pitch requirements by introducing virtual grid lines that operate at a higher resolution (e.g., 1/2 or 1/3 of the nominal minimum pitch). This allows the standard cell to be divided into smaller routing segments that can be precisely positioned without requiring the overall cell height to be an integral multiple of the nominal pitch, thus reducing die size while maintaining manufacturing compliance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Virtual grid lines serve as an intermediary between the standard cell boundaries and the manufacturing pitch constraints. These virtual grid lines provide a finer reference system that enables precise routing placement without requiring the cell itself to conform to integral multiple pitch requirements, thereby achieving both design flexibility and manufacturing compliance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If standard cell size is increased to accommodate integral multiple pitch requirements, then manufacturing compliance is achieved, but overall die size increases

Engineering Contradiction:
Improvemanufacturing complianceVSAvoidstandard cell size
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent introduces an additional dimensional layer by implementing virtual grid lines at a finer resolution than the nominal minimum pitch. This allows routing to be precisely positioned within the standard cell without requiring the cell dimensions to be expanded to integral multiples of the nominal pitch, thereby maintaining manufacturing precision while minimizing cell size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If virtual grid lines are used for routing, then routing precision is improved, but layout complexity increases

Engineering Contradiction:
Improverouting precisionVSAvoidlayout complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The virtual grid line system serves multiple functions simultaneously: it provides precise routing alignment, enables non-integral pitch standard cell design, and maintains compatibility with existing manufacturing processes. This multi-functionality reduces the need for separate complex alignment systems, thereby managing layout complexity while achieving high routing precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250061260A1Integrated circuit having non-integral multiple pitch
Publication Date: 2025.02.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250061260A1 patent drawing
  • US20250061260A1 patent drawing
  • US20250061260A1 patent drawing

AI summary

An integrated circuit includes a plurality of routing lines extending along a first direction, the plurality of routing lines being separated in the first direction by integral multiples of a nominal minimum pitch. The integrated circuit includes a plurality of standard cells, at least one of the plurality of standard cells having a first boundary coinciding with a routing line of the plurality of routing lines, and a second boundary offset from each of the plurality of routing lines.