Standard Cell Pin Layout for Wire-Cut-Free Interconnect Routing

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Solution Overview

Problem

The increasing demand for scaled integrated circuits poses challenges in routing interconnects due to restrictions imposed by wire cuts placed by electronic design automation tools, which limit the availability of area for interconnects in integrated circuit layout designs.

Innovation Solution

Modifying the dimensions of standard cell pins to increase their distance from boundaries, thereby avoiding the placement of wire cuts and providing additional area for interconnect routing, while ensuring a minimum distance to prevent electrical shorts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wire cuts are placed by electronic design automation tools to prevent electrical shorts, then electrical integrity is improved, but the available area for interconnect routing is reduced

Engineering Contradiction:
Improveelectrical integrityVSAvoidavailable area for interconnect routing
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The pin dimensions are modified in advance during the design phase to anticipate and prevent the placement of wire cuts. By adjusting pin dimensions before routing, the design creates sufficient spacing that eliminates the need for wire cuts, thereby preserving routing area while maintaining electrical integrity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The physical dimensions of standard cell pins are changed to increase spacing between adjacent pins. This parameter modification (increasing distance between pins) prevents electrical shorts without requiring wire cuts, thus resolving the contradiction between reliability and available routing area

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If pin dimensions are increased to provide more spacing, then area for interconnect routing is improved, but the risk of electrical shorts increases

Engineering Contradiction:
Improvearea for interconnect routingVSAvoidelectrical integrity
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The pin dimensions are systematically adjusted to achieve optimal spacing that simultaneously provides sufficient routing area and maintains adequate separation to prevent electrical shorts. The parameter change is calculated to satisfy both competing requirements

Inventive Principle:
Principle #35Parameter changes

3Reliability

If wire cuts are placed to ensure electrical integrity, then reliability is improved, but interconnect routing complexity increases

Engineering Contradiction:
Improveelectrical integrityVSAvoidinterconnect routing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By modifying pin dimensions before the routing process begins, the design eliminates the need for wire cuts that would complicate routing. This preliminary dimension adjustment simplifies the subsequent interconnect routing process while maintaining electrical integrity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Changing the pin dimension parameters creates a design that is inherently easier to route by eliminating constraints (wire cuts), thereby reducing routing complexity while preserving reliability

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240354487A1Pin modification for standard cells
Publication Date: 2024.10.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240354487A1 patent drawing
  • US20240354487A1 patent drawing
  • US20240354487A1 patent drawing

AI summary

The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.