Standard Cell Placement Using Boundary Compatibility Data
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Solution Overview
Problem
As semiconductor integrated circuits shrink in size, existing automated tools for generating layouts face challenges in maximizing functionality within smaller areas due to rigid design rules that restrict the placement of standard cells, limiting the density of functional components.
Innovation Solution
Introducing standard cells with incompatible boundaries, where compatibility information is used to guide the placement of cells, allowing for relaxed design rules and increased density by using filler cells to match dopant implantations and layer positions, ensuring no abutting cells have incompatible boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If standard cells are arranged with uniform boundaries allowing any cell to abut any other cell, then ease of automated placement is improved, but area efficiency deteriorates due to rigid design rules preventing tighter packing
Solution Approach 1:
The patent applies parameter changes by transitioning from uniform boundary parameters to variable boundary parameters. Each standard cell is assigned a boundary type (A or B) that changes the placement rules. This parameter variation allows the automated tool to make intelligent placement decisions that reduce white space while maintaining design rule compliance, thereby improving area efficiency without sacrificing ease of automated placement.
Solution Approach 2:
The patent introduces dynamics by making boundary compatibility a dynamic constraint in the placement algorithm. Rather than static uniform boundaries, the system dynamically evaluates boundary types (A or B) of adjacent cells during placement. This dynamic approach allows the automated tool to adapt placement decisions based on boundary compatibility, optimizing area utilization while maintaining ease of operation through automated conflict resolution.
2Area of stationary object
If design rules are relaxed to allow higher density of functional components, then area efficiency is improved, but manufacturing precision deteriorates due to potential interactions between adjacent cell elements
Solution Approach 1:
The patent applies local quality by assigning different boundary characteristics (types A and B) to different sides of standard cells based on local manufacturing constraints. Each boundary type represents specific local quality requirements - for example, boundary type A may require minimum spacing for polysilicon while boundary type B may have different requirements. This localized boundary quality approach allows tight packing in compatible regions while maintaining manufacturing precision through targeted constraint application at each boundary interface.
3Manufacturing precision
If standard cells are configured with orientation restrictions to prevent incompatible boundary abutments, then manufacturing precision is improved, but device complexity increases due to limited placement flexibility
Solution Approach 1:
The patent applies inversion by reversing the traditional approach: instead of restricting cell orientations to prevent incompatible boundaries, the system restricts which boundary types can abut each other while allowing flexible cell orientations. This inverted approach maintains manufacturing precision through boundary type compatibility rules (A next to B, not A next to A) while significantly reducing device complexity by eliminating orientation constraints, thereby improving placement flexibility.
Data Source
AI summary
A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit elements, providing a cell library defining a plurality of standard cells, each standard cell representing a potential component for forming the integrated circuit, providing compatibility information indicative of the compatibility of the boundaries of the standard cells, and generating a placement of standard cells in dependence on the functional data and the compatibility information to produce the layout such that no abutting cells have incompatible boundaries.