Integrated Standard Cell Layout for Mixed PMOS Thresholds
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Solution Overview
Problem
Integrated circuits face space congestion and performance issues when trying to combine silicon germanium channel transistors with different voltage thresholds within a single circuit, as existing arrangements either consume space or lead to performance drops due to transistor interactions.
Innovation Solution
The integration of standard cells with silicon germanium channel PMOS transistors and silicon channel PMOS transistors adjacent to each other, using semiconductor connection regions with insulating gates to minimize stress relaxation and performance loss, and employing filling cells to maintain performance while reducing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If silicon germanium channel transistors and silicon channel transistors are placed adjacent to each other, then space utilization is improved and surface congestion is reduced, but performance drops due to stress relaxation and transistor interactions
Solution Approach 1:
The patent introduces filling cells as intermediary elements between silicon germanium channel transistors and silicon channel transistors. These filling cells contain semiconductor material that maintains stress continuity while electrically isolating the different transistor types, thereby preventing performance degradation while allowing adjacent placement of diverse transistors
Solution Approach 2:
The patent segments the standard cell layout into distinct regions with different transistor types separated by filling cells. This segmentation allows each transistor type to maintain its optimal stress conditions while still achieving overall space efficiency through compact arrangement of the segmented units
2Adaptability or versatility
If standard cells with different transistor types are integrated, then adaptability and versatility are improved, but device complexity increases
Solution Approach 1:
The patent creates a universal standard cell framework that can accommodate multiple transistor types (silicon germanium channel and silicon channel) through the use of filling cells. This multi-functional approach allows the same cell structure to support different transistor configurations without requiring entirely separate design methodologies for each transistor type
Data Source
AI summary
An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.