Standard Cell Buried Power Rail Layout for Larger Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing standard cell method for semiconductor integrated circuits restricts the size of transistors due to the placement of buried power rails, making it difficult to increase transistor size without compromising the layout.
Innovation Solution
The semiconductor integrated circuit device incorporates buried power lines in the interconnect layer, strategically positioning them to allow for increased transistor size by spacing them from transistors and placing them closer to the center of standard cells, enabling expansion of transistor range without obstructing transistor placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buried power rails are laid along upper and lower ends of a standard cell, then power supply is provided to standard cells, but transistors cannot be placed at the upper and lower ends of the standard cell, making it difficult to increase transistor size
Solution Approach 1:
The patent changes the spatial arrangement by moving the buried power line from the edge position (upper/lower ends) to the center position of the standard cell in the planar view. This dimensional repositioning allows transistors to be placed at the upper and lower ends, enabling transistor size expansion while maintaining power supply functionality through the centrally located buried power line.
Solution Approach 2:
The patent introduces asymmetric layout design where the buried power line is positioned closer to the center of the standard cell rather than symmetrically at the edges. This asymmetric positioning creates available space at the upper and lower ends for transistor placement, resolving the contradiction between power supply requirements and transistor size expansion.
2Area of moving object
If transistors are placed at upper and lower ends of standard cell, then transistor size can be increased, but buried power rails cannot be laid in those regions
Solution Approach 1:
The patent resolves the layout constraint by repositioning the buried power line to the center of the standard cell in the planar view, creating a new spatial configuration. This allows transistors to occupy the upper and lower ends while the centrally located buried power line provides power supply, achieving both transistor size increase and manufacturable layout.
3Area of moving object
If buried power lines are spaced from transistors and located closer to center of standard cell, then transistor size can be expanded, but power line placement becomes more complex
Solution Approach 1:
The patent simplifies the overall device complexity by introducing a regular asymmetric pattern where buried power lines are consistently positioned at the center of each standard cell. This standardized asymmetric placement, while different from conventional edge positioning, creates a predictable and manufacturable layout that facilitates transistor size expansion without significantly increasing fabrication complexity.
Data Source
AI summary
In a semiconductor integrated circuit device using buried power lines, a standard cell includes: a first buried power line extending in the X direction and supplying a first power supply voltage; a second buried power line extending in the X direction and supplying a second power supply voltage; and a first transistor connected to the first power line. The first buried power line is spaced from the first transistor in planar view and located closer to the center of the standard cell than the first transistor in the Y direction.