Standard Cell Power Supply Line Layout for Speed and Integration
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Solution Overview
Problem
Conventional semiconductor device configurations face challenges in achieving both higher speeds and higher integration due to the difficulty in widening power supply lines and arranging multiple transistors vertically, which increases power supply noise and complicates interconnect layouts.
Innovation Solution
The semiconductor device employs a power supply line configuration with separate lower and upper layer interconnects, where the lower layer interconnect extends along the boundary of standard cells and the upper layer interconnect is positioned inside, allowing for increased electric current paths without widening the power supply line, thus enabling higher speeds and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the line width of power supply line is increased to reduce IR-Drop, then the resistance value decreases and power supply noise is reduced, but it becomes difficult to secure intervals between interconnects and the layout becomes more complex
Solution Approach 1:
The patent applies dimensionality change by transitioning from a single-layer power supply line to a multi-layer interconnect structure. Specifically, it uses a first power supply line in a first metal layer and a second power supply line in a second metal layer, thereby adding a vertical dimension to the power supply path. This resolves the contradiction by achieving lower effective resistance and reduced IR-Drop through layered configuration without requiring excessive lateral width that would complicate the layout.
Solution Approach 2:
The patent segments the power supply function into multiple independent interconnect lines distributed across different metal layers. Instead of relying on a single wide power supply line, it divides the power supply path into multiple narrower lines (first power supply line and second power supply line) that are distributed vertically across layers, simplifying the lateral layout while maintaining electrical performance.
2Productivity
If four transistors are arranged in a row in vertical direction to achieve higher integration, then the integration density increases, but the number of interconnects increases and the interconnect layout becomes more complicated
Solution Approach 1:
The patent applies dimensionality change by utilizing multiple metal layers to route interconnects. Instead of arranging all interconnects in the planar direction which complicates the layout, it distributes interconnects across different vertical layers (first metal layer and second metal layer), thereby achieving high integration density while maintaining simplified interconnect routing through the vertical dimension.
3Speed
If power supply lines are widened for higher speeds, then the current carrying capacity increases, but it becomes difficult to arrange multiple transistors vertically for higher integration
Solution Approach 1:
The patent resolves this contradiction by moving the power supply lines to different metal layers. The first power supply line is placed in the first metal layer and the second power supply line in the second metal layer, allowing both lines to coexist without lateral interference. This vertical separation enables sufficient current carrying capacity for high-speed operation while preserving lateral space for arranging multiple transistors vertically to achieve high integration density.
Data Source
AI summary
CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration.