Standard-Cell Power Routing for Lower RC Parasitics
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Solution Overview
Problem
As integrated circuit (IC) devices are miniaturized to increase transistor counts, interconnect resistances rise due to smaller dimensions, and parasitic capacitances increase, leading to reduced drive current and performance issues, particularly at higher frequencies.
Innovation Solution
The implementation of additional power supply lines to reduce interconnect resistances, strategic deployment of supply lines as shielding between signal lines, and splitting shared transistor connections to provide parallel current paths, thereby mitigating resistance bottlenecks and RC delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If standard cells are packed into less area to increase transistor counts, then device density is improved, but interconnect resistances increase and parasitic capacitances increase
Solution Approach 1:
The power supply network is segmented into multiple parallel interconnect lines (first and second interconnect lines) that independently supply power to transistor sources. This segmentation reduces the resistance of each individual interconnect path, allowing higher transistor density without proportionally increasing interconnect resistance.
Solution Approach 2:
The patent introduces a vertical dimension to power delivery by stacking interconnect lines at different levels (first interconnect line at first level, second interconnect line at second level) and using vias to connect them. This three-dimensional power distribution reduces current crowding and resistance in the planar direction, enabling higher device density.
2Quantity of substance
If standard cells are packed into less area to increase transistor counts, then device density is improved, but parasitic capacitances increase
Solution Approach 1:
The power supply is divided into multiple parallel interconnect paths with separate vias, which reduces the capacitance seen by each transistor. This segmentation of the power network reduces parasitic capacitance effects while maintaining high transistor density.
3Area of stationary object
If interconnect widths are decreased to maintain cell dimensions, then area is reduced, but interconnect resistances increase
Solution Approach 1:
The patent uses multiple interconnect levels stacked vertically with vias connecting them, effectively increasing the cross-sectional area for current flow without increasing the planar cell footprint. This 3D interconnect approach reduces resistance while maintaining small cell dimensions.
Solution Approach 2:
Multiple interconnect lines and vias are merged into a parallel power delivery network, combining their conductive cross-sections to achieve lower equivalent resistance while keeping individual interconnect widths small to maintain cell area.
4Power
If additional power supply lines are added to reduce interconnect resistances, then drive current is improved, but device complexity increases
Solution Approach 1:
The additional interconnect lines and vias serve multiple functions: they reduce power delivery resistance, provide parasitic capacitance shielding, and can be integrated with existing CMOS fabrication processes. This multi-functionality justifies the increased structural complexity by delivering multiple performance benefits simultaneously.
Data Source
AI summary
An integrated circuit (IC) device may include standard cells with multiple parallel paths interconnecting transistors at a device level and over a transistor, in a higher layer of an interconnect structure. The parallel paths may include multiple power supply via contacts on a transistor source structure and multiple supply interconnect lines over the transistor and coupling the transistor to an associated power supply. The parallel paths may include multiple output via contacts on an integrated transistor drain structure and multiple output interconnect lines over a complementary transistor device. The parallel paths may include separate, rather than shared or integrated, adjacent source structures coupled to a same power supply.