Standard Cell Routing Resources via Power Bus Removal
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Solution Overview
Problem
In integrated circuit (IC) design, standard cells often have limited signal routing resources due to the presence of power and ground buses on metal layers, which complicates signal routing between closely clustered and small-sized components, necessitating a method to increase available routing area without substantial redesign.
Innovation Solution
The approach involves identifying and removing power and ground buses from a metal layer in standard cell descriptions, re-routing connections to alternative layers, thereby freeing up metal layer area for signal routing while maintaining electrical connectivity, and re-establishing power and ground connections during chip design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power and ground buses are present on metal layers in standard cells, then electrical connectivity is maintained, but signal routing resources are reduced
Solution Approach 1:
The patent moves power and ground connections from the two-dimensional metal layer plane to the third dimension by routing them through vertical vias to alternative metal layers. This dimensional transition frees up the original metal layer area for signal routing while maintaining electrical connectivity through the vertical via paths.
Solution Approach 2:
The patent introduces vias as intermediary elements that transfer power and ground connections between different metal layers. These vias act as mediators that maintain electrical connectivity while allowing the original metal layer to be dedicated to signal routing, thus resolving the conflict between connectivity and routing area.
2Quantity of substance
If standard cells are closely clustered and small-sized, then integration density is increased, but signal routing complexity increases
Solution Approach 1:
By routing power and ground connections to alternative metal layers through vias, the patent reduces the congestion on metal layers within closely clustered standard cells. This dimensional redistribution simplifies signal routing paths while maintaining high component density.
3Area of stationary object
If metal layer area is increased for signal routing, then routing resources are improved, but power and ground connections must be reconfigured
Solution Approach 1:
The patent uses vias as intermediary elements to automatically manage the reconfiguration of power and ground connections. When standard cells are instantiated, the EDA tool automatically routes connections through vias to alternative metal layers, reducing the manual reconfiguration burden while maximizing routing area.
Solution Approach 2:
The patent changes the layer parameter for power and ground connections from the original metal layer to alternative metal layers. This parameter change is managed through EDA tool automation, which updates the connection parameters without requiring substantial manual rework, thus achieving area increase with minimal complexity.
Data Source
AI summary
Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).