Standard Cell Layout Across Unequal Row Heights for Drive Strength
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Solution Overview
Problem
Existing semiconductor integrated circuit devices face challenges with increased off-current and power consumption due to excessive transistor scaling, and there is a need for a layout structure that optimizes standard cells lying astride multiple standard cell rows of different heights to enhance integration and performance.
Innovation Solution
A semiconductor integrated circuit device is designed with a double-height cell placed astride two standard cell rows of different heights, where the first logic circuit is formed in one cell row and the second logic circuit is formed in the other, allowing for increased channel width of transistors in one row compared to the other, thereby reducing input capacity and enhancing output drive capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are excessively scaled to improve integration degree and operating speed, then device size is reduced, but off current increases and power consumption increases
Solution Approach 1:
The patent applies local quality by creating different cell row heights (first cell row with height H1, second cell row with height H2 where H2 > H1) to provide different channel widths for transistors in different locations. This allows specific transistors to have larger channel widths for lower off-current while maintaining overall device integration.
Solution Approach 2:
The patent transitions from a uniform two-dimensional standard cell layout to a three-dimensional structure with varying cell row heights. Double-height cells spanning multiple rows and different height cell rows create vertical dimensionality, enabling transistors with different channel widths within the same logical cell structure.
2Area of moving object
If standard cells are placed astride multiple standard cell rows to improve integration, then area utilization increases, but layout complexity increases
Solution Approach 1:
The patent segments the cell structure into different height regions (first cell row height H1, second cell row height H2) with clear boundaries. Double-height cells are explicitly defined to span specific rows, creating a modular segmented layout that improves area utilization while managing complexity through structured division.
Solution Approach 2:
The patent introduces asymmetric cell row heights where the second cell row has greater height than the first cell row. This asymmetric structure allows double-height cells to be placed strategically astride rows of different heights, optimizing area utilization while the asymmetry itself becomes part of the standardized layout pattern.
3Power
If transistor channel width is increased to improve output drive capability, then output drive capability increases, but input capacity increases
Solution Approach 1:
The patent applies local quality by positioning transistors with different channel widths (due to different cell row heights) in specific locations within the logic circuit. The second cell row with greater height H2 provides transistors with larger channel widths for high output drive capability, while the first cell row with height H1 provides transistors with smaller channel widths for low input capacity, allowing optimization of both parameters in different locations.
Data Source
AI summary
A layout structure of a standard cell lying astride standard cell rows different in height is provided. A double-height cell is formed astride first and second cell rows. The height of the second cell is greater than the height of the first cell. The double-height cell includes a first logic circuit that receives an input signal and outputs a signal to an internal node and a second logic circuit that receives the signal from the internal node and outputs an output signal. Transistors constituting the first logic circuit are formed in a region of the first cell row, and transistors constituting the second logic circuit are formed in a region of the second cell row.