Standard Cell Layout With Shared Source/Drain Contacts
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Solution Overview
Problem
As semiconductor manufacturing processes are miniaturized, the complexity of connecting source/drain contacts in integrated circuits increases, leading to reduced stability, increased pin congestion, and limited freedom in metal line routing.
Innovation Solution
The integrated circuit design incorporates a novel layout where multiple source/drain contacts are connected through a reduced number of layers, specifically connecting transistors via a single source/drain contact, thereby reducing the overall height and improving process stability while increasing metal line flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple source/drain contacts are connected through multiple layers, then the connection reliability is improved, but the device complexity and pin congestion increase
Solution Approach 1:
The patent merges multiple source/drain contacts into a single contact structure that connects multiple transistors simultaneously. This is achieved by designing a shared contact that extends under multiple gate structures, allowing multiple transistors to be connected through one contact rather than requiring separate contacts for each transistor, thereby reducing overall device complexity while maintaining connection reliability
Solution Approach 2:
The shared source/drain contact serves multiple functions by connecting multiple transistors at once. This universal contact structure acts as a common electrical pathway for multiple device instances, reducing the number of individual connections needed and decreasing pin congestion in the overall circuit layout
2Reliability
If multiple source/drain contacts are connected through multiple layers, then the connection reliability is improved, but the manufacturing process stability deteriorates
Solution Approach 1:
The patent extracts the complexity of multi-layer connections by implementing a single-layer shared contact approach. Instead of creating multiple separate contact vias through different metal layers, the design uses one contact structure that achieves the same connectivity function, thereby simplifying the manufacturing process and improving process stability while maintaining reliable electrical connections
3Adaptability or versatility
If the number of source/drain contacts is increased, then the transistor connectivity is improved, but the metal line routing freedom is reduced
Solution Approach 1:
The patent merges the routing paths for multiple transistors into a single shared contact structure. By combining multiple connection functions into one contact, the design reduces the number of metal line segments needed and increases routing freedom, as fewer discrete connections need to be established through the metal interconnect layers
Data Source
AI summary
An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.


