Standard Cell Layout for Mixed SiGe and Silicon PMOS Thresholds
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Solution Overview
Problem
Integrated circuits face space congestion and performance issues when trying to combine silicon germanium channel transistors with different voltage thresholds on a single substrate, as existing arrangements either consume space or cause performance drops due to transistor interactions.
Innovation Solution
The integration of standard cells with silicon germanium channel PMOS transistors and silicon channel PMOS transistors adjacent to each other, using semiconductor connection regions with insulating gates to minimize stress relaxation and performance loss, and employing filling cells to maintain performance while reducing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If silicon germanium channel transistors and silicon channel transistors are placed adjacent to each other, then space efficiency is improved, but performance drops due to stress relaxation at the interface
Solution Approach 1:
A filling cell containing a filling region is inserted between the silicon germanium channel transistor and the silicon channel transistor. The filling region acts as an intermediary that maintains the stress state of the silicon germanium channel by providing a compatible material interface, thereby preventing stress relaxation while enabling close placement of different transistor types.
2Adaptability or versatility
If standard cells with different transistor types are mixed, then device versatility is improved, but manufacturing complexity increases
Solution Approach 1:
The standard cell is segmented into distinct functional regions: a first region containing silicon germanium channel transistors, a second region containing silicon channel transistors, and a filling region separating them. This segmentation allows each region to be optimized independently while maintaining a standardized overall cell structure that simplifies manufacturing processes.
Solution Approach 2:
Different regions within the standard cell are assigned different material compositions and structural properties tailored to their specific functions. The silicon germanium channel region is optimized for high-speed performance, the silicon channel region for low leakage, and the filling region for stress maintenance, allowing each local area to have the quality needed for its purpose.
Data Source
AI summary
An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.