Standard Cell Buried Interconnect Layout for Higher Signal Density
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Solution Overview
Problem
The existing standard cell method for semiconductor integrated circuits limits the number of buried signal lines that can be laid in the interconnect layer due to the placement of fin transistors, resulting in increased area requirements for the semiconductor device.
Innovation Solution
The configuration includes standard cells with transistors having channel portions extending in one direction and signal lines in the buried interconnect layer overlapping with the channel portions in a perpendicular direction, allowing for multiple signal lines to be laid without expanding the device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fin transistors are placed in the substrate to perform logical functions, then the logical function is achieved, but the number of signal lines that can be laid in the buried interconnect layer is limited
Solution Approach 1:
The patent applies dimensionality change by allowing signal lines to overlap with transistor channel portions in the vertical dimension (second direction perpendicular to the first direction). This enables multiple signal lines to be laid in the buried interconnect layer without increasing the planar area of the standard cell, effectively utilizing the third dimension to increase routing capacity.
Solution Approach 2:
The patent makes the buried interconnect layer serve multiple functions: it not only provides power supply through buried power rails but also carries multiple signal lines simultaneously. This multi-functionality allows the same interconnect layer to handle both power distribution and signal routing, increasing the number of usable signal lines without requiring additional layers or area.
2Quantity of substance
If the area of the standard cell is increased to lay more signal lines in the buried interconnect layer, then the number of buried signal lines increases, but the area of the semiconductor integrated circuit device increases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension for signal line routing. Signal lines are allowed to overlap with transistor channel portions in the second direction (vertical), enabling more signal lines to be packed into the same planar footprint without increasing the overall device area.
Solution Approach 2:
The patent applies local quality by creating specific regions within the standard cell designated for signal line routing. Certain areas are optimized for carrying multiple buried signal lines, while other areas maintain transistor functionality, allowing dense signal routing in specific locations without compromising overall device performance or increasing total area.
Data Source
AI summary
In a semiconductor integrated circuit device, a plurality of standard cells arranged in an X direction include a first standard cell having a logical function and including a transistor having a channel portion extending in the X direction, and a second standard cell including a signal line placed to extend in the X direction. The signal line is formed in a buried interconnect layer, and has an overlap with the channel portion at a position in a Y direction.