Standard Cell Source Edge Abutment for Chip Area Optimization
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Solution Overview
Problem
In integrated circuit design, the use of filler cells to separate standard cells results in wastage of chip area due to the inability to abut certain types of standard cells, leading to inefficient layout and routing.
Innovation Solution
The design scheme allows for standard cells with specific edge configurations, including source and drain edges, where source edges can abut each other, eliminating the need for filler cells by merging dummy gates (PODEs) and aligning power supply voltages, thereby optimizing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If filler cells are inserted between standard cells to separate them, then the reliability of cell separation is improved, but the chip area is wasted
Solution Approach 1:
The patent extracts and removes the filler cells from the standard cell layout. By eliminating the filler cells that were previously inserted between standard cells for separation, the invention achieves both cell separation through direct abutting and maximizes chip area utilization without wasted space.
2Area of stationary object
If standard cells are placed as parallel rows with abutted edges, then the chip area utilization is improved, but the manufacturing complexity increases due to alignment requirements
Solution Approach 1:
The patent segments the standard cell edges into source edges and non-source edges, with specific orientation requirements. By dividing the cell boundaries into functionally distinct segments and prescribing their orientations, the invention enables straightforward abutting placement that simplifies manufacturing alignment while maximizing chip area utilization.
3Ease of operation
If source edges of all standard cells are oriented to face the same direction, then the ease of placement and routing is improved, but the adaptability to different cell types is reduced
Solution Approach 1:
The patent establishes universal orientation rules for source edges that apply across all standard cell types. By defining that source edges must face the same direction regardless of cell type, the invention creates a unified placement and routing framework that simplifies operations while maintaining adaptability through the consistent application of the rule to diverse cell types.
Data Source
AI summary
A die includes a plurality of rows of standard cells. Each of all standard cells in the plurality of rows of standard cells includes a transistor and a source edge, wherein a source region of the transistor is adjacent to the source edge. No drain region of any transistor in the each of all standard cells is adjacent to the source region.