Standard Cell Layout With Individual Source Regions for Lower Parasitics
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Solution Overview
Problem
The miniaturization of semiconductor manufacturing processes in integrated circuits increases manufacturing difficulty and limits performance improvement, particularly due to the complexity of standard cell configurations and reduced sizes, which affect the efficiency and speed of integrated circuits.
Innovation Solution
The introduction of a cell design with individual source regions and a source isolation structure, specifically an SDB structure, which separates source regions and reduces resistance without requiring additional process changes, enhancing the layout and electrical connectivity of gate lines, metal lines, and contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor manufacturing processes are miniaturized to reduce standard cell size, then integration density increases, but manufacturing difficulty increases and performance improvement is limited
Solution Approach 1:
The source region is divided into multiple individual source regions (first source region and second source region) corresponding to different gate lines. This segmentation allows each source region to be independently formed and contacted, simplifying the manufacturing process by enabling separate processing steps for each region rather than requiring complex simultaneous processing of miniaturized structures.
Solution Approach 2:
The patent introduces a vertical dimension by forming source regions at different depths or positions relative to gate lines. The first source region is formed in association with a first gate line and the second source region with a second gate line, creating a three-dimensional arrangement that increases integration density without proportionally increasing manufacturing complexity.
2Area of moving object
If standard cell size is reduced, then integration density increases, but performance improvement is limited
Solution Approach 1:
By segmenting the source region into multiple independent source regions, each can be optimized for its specific function. The first source region connects to the first gate line and the second source region to the second gate line, allowing independent optimization of electrical characteristics for each transistor, thereby maintaining high performance despite reduced cell size.
Solution Approach 2:
Different source regions can have different local properties optimized for their specific requirements. The first source region may have different doping concentration, depth, or geometry compared to the second source region, allowing each to be locally optimized for its associated gate line's function, thus maintaining overall cell performance.
3Device complexity
If source regions are shared between adjacent gate lines, then device complexity is reduced, but parasitic capacitance increases and operating speed decreases
Solution Approach 1:
The source region is segmented into separate first and second source regions, each exclusively associated with a specific gate line. This physical separation eliminates the parasitic capacitance that would exist between source regions of different gate lines, thereby increasing operating speed while maintaining manageable device complexity through systematic segmentation.
Solution Approach 2:
The harmful parasitic capacitance effect is extracted or eliminated by physically separating the source regions. By taking out the shared source region configuration and replacing it with individual source regions, the parasitic capacitance between adjacent transistors is removed, improving operating speed.
Data Source
AI summary
A cell including individual source regions includes active regions extending in a first direction and being spaced apart from each other in a second direction different from the first direction, gate lines extending across the active regions in the second direction and being spaced apart from each other in the first direction, first contacts arranged on both sides of each of the gate lines in the first direction and connected to the active regions, metal lines arranged over the gate lines and the first contacts, the metal lines extending in the first direction and being spaced apart from each other in the second direction, second contacts connecting the gate lines to the metal lines, and vias connecting the first contacts to the metal lines.