Standard Cell Spacing Quality Checking Method

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Solution Overview

Problem

Automated tools lack a systematic approach for checking standard cell quality, particularly in terms of spacing, leading to potential issues in IC design and manufacturing, such as increased area requirements and reduced performance.

Innovation Solution

A standardized cell level spacing quality checking methodology using a scoring system to evaluate and optimize cell design quality, incorporating automated processes to assess cell-to-cell spacing and provide feedback for design refinement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If automated tools are used for standard cell quality checking, then productivity is improved, but measurement precision and manufacturing precision deteriorate due to lack of systematic approach

Engineering Contradiction:
Improvequality checking efficiencyVSAvoidcell spacing quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The quality checking process is segmented into multiple independent check types: spacing checks, power grid checks, signal integrity checks, and performance checks. Each check type is handled by a dedicated module that evaluates specific aspects of standard cell design, allowing automated systematic verification of all critical parameters.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system provides automated feedback by comparing actual cell spacing and design parameters against predefined design rules and thresholds. When violations are detected, the system generates detailed reports indicating the nature and location of issues, enabling iterative refinement of the design to achieve both automation and precision.

Inventive Principle:
Principle #23Feedback

2Manufacturing precision

If manual quality checking is performed, then measurement precision is maintained, but productivity deteriorates due to time-consuming processes

Engineering Contradiction:
Improvecell spacing qualityVSAvoiddesign turnaround time
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The quality checking system performs self-verification by automatically evaluating standard cell designs against embedded design rules without requiring manual intervention. The system independently checks spacing, power grid, signal integrity, and performance parameters, providing comprehensive quality assurance that scales efficiently with design complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system performs quality checks during the design phase before manufacturing occurs. By validating cell spacing, power grid configurations, and signal integrity in advance, the system prevents defects from propagating to later stages, reducing rework and accelerating the overall design-to-manufacturing timeline.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If standardized spacing checks are implemented, then manufacturing precision is improved, but device complexity increases due to additional checking processes

Engineering Contradiction:
Improvecell-to-cell spacingVSAvoidquality checking methodology
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The quality checking framework is designed as a universal system that handles multiple check types through a unified architecture. A single platform performs spacing verification, power grid analysis, signal integrity checking, and performance evaluation, eliminating the need for separate specialized tools and reducing overall system complexity despite the comprehensive coverage.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250111123A1Standard cell spacing quality checking
Publication Date: 2025.04.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250111123A1 patent drawing
  • US20250111123A1 patent drawing
  • US20250111123A1 patent drawing

AI summary

A method for checking standard cell spacing in a design includes providing a first standard cell. A cell environment of the first standard cell is determined and a first feasible distance between a first boundary of the standard cell and a boundary of a first adjacent cell based on the cell environment is determined. A second feasible distance between a second boundary of the standard cell and a boundary of a second adjacent cell based on the cell environment is determined. A feasible spacing between the first standard cell and a second standard cell is provided, and the feasible spacing is evaluated based on the first feasible distance, the second feasible distance and a cell pitch of the first standard cell. An integrated circuit is fabricated that includes the first standard cell in response on the evaluating.