Standard Cell Layout With Variable Routing Pitch for Dense Interconnects
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Solution Overview
Problem
As demand for high performance, high speed, and multifunctionality in semiconductor devices increases, there is a need for improved integration and reliability in semiconductor device layout designs, particularly in the efficient routing of interconnection lines to connect semiconductor devices effectively.
Innovation Solution
The semiconductor device incorporates standard cells arranged in specific directions with varying pitches for interconnection lines, along with filler cells, to enhance integration and reliability, utilizing a design system that includes a processor, storage device, and modules for placement and routing to optimize circuit function blocks with different cell libraries and routing tracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard cells are arranged with uniform interconnection line pitches, then manufacturing is simpler, but routability and integration density are reduced
Solution Approach 1:
The patent applies local quality by varying the pitch of interconnection lines in different standard cell rows. Specifically, first standard cells have interconnection lines with a first pitch, while second standard cells have interconnection lines with a second pitch different from the first. This allows each region to be optimized for its specific routing needs, improving overall integration density while maintaining manufacturability through localized rather than global uniformity.
2Adaptability or versatility
If interconnection lines have varying pitches, then routability improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the standard cell array into distinct rows or groups, where each segment (first standard cells, second standard cells) has a uniform interconnection line pitch within that segment. This segmentation allows varying pitches across different segments to improve routability, while each segment maintains internal uniformity that simplifies manufacturing. The segmentation creates a balance between adaptability and manufacturability.
3Productivity
If filler cells are added between standard cells, then integration density improves, but device complexity increases
Solution Approach 1:
The patent merges filler cells with the functional standard cells to form an integrated array structure. The filler cells are positioned between first and second standard cells, and all cells (functional and filler) share the same gate structure configuration. This merging approach allows the filler cells to contribute to the overall integration density while maintaining structural uniformity that reduces device complexity.
Data Source
AI summary
A semiconductor device includes standard cells in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, and filler cells between ones of the standard cells. Each of the standard cells includes an active region, a gate structure that intersects the active region, source/drain regions on the active region on both sides of the gate structure, and interconnection lines. Each of the filler cells includes a filler active region and a filler gate structure that intersects the filler active region. The standard cells include first to third standard cells in first to third rows sequentially in the second direction, respectively. First interconnection lines are arranged with a first pitch, second interconnection lines are arranged with a second pitch, and third interconnection lines are arranged with a third pitch different from the first and second pitches.