Standard Cell Power Rail Layout to Prevent Via Bridging
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor devices lead to higher yield loss, reduced reliability of electrical interconnections, and low testing coverage, necessitating improvements in device structure and manufacturing methods to enhance robustness, reduce manufacturing costs, and shorten processing time.
Innovation Solution
The implementation of specific design layouts and biasing path configurations for standard cells in semiconductor devices, including unique arrangements of conductive vias and power rails, to minimize defects and optimize manufacturing efficiency, such as ensuring adequate pitch between conductive vias and power rails to prevent bridging issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If functional density is increased and geometric size is decreased, then device capability is improved, but manufacturing complexity increases and reliability decreases
Solution Approach 1:
The patent divides the power supply routing into separate dedicated lanes (first power supply lane and second power supply lane) that are spatially segregated and do not share common conductive vias. This segmentation prevents interference between adjacent cells and eliminates bridging risks, thereby maintaining high functional density while improving electrical interconnection reliability through physical separation of power supply paths.
2Volume of moving object
If device size is miniaturized, then device capability is improved, but manufacturing complexity and yield loss increase
Solution Approach 1:
The patent establishes specific design rules and layout constraints during the design phase that pre-prevent manufacturing defects. By mandating separate power supply lanes with dedicated conductive vias and prohibiting shared via usage, the design inherently prevents bridging issues and manufacturing variability, simplifying the manufacturing process and improving yield despite miniaturization.
3Productivity
If standard cells are placed closer together, then manufacturing efficiency is improved, but interference between adjacent cells increases
Solution Approach 1:
The patent extracts the power supply routing function from the shared interconnect structure and creates dedicated power supply lanes with专属 conductive vias for each cell. This separation removes the interference mechanism between adjacent cells, allowing standard cells to be placed closer together without risking signal interference or bridging, thereby improving manufacturing efficiency while eliminating harmful interactions.
Data Source
AI summary
A layout method and a layout system are disclosed. The layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region, a second source/drain region and a gate electrode, wherein the gate electrode define an odd-numbered track and an even-numbered track. The first cell also includes a first power rail, a first conductive via within the odd-numbered track, a second power rail and a second conductive via within the even-numbered track. The first source/drain region is electrically connected to the first power rail through the first conducive via, and the second source/drain region is electrically connected to the second power rail through the second conducive via.