Standard Cell Via Layout for Lower Routing Congestion
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Solution Overview
Problem
The increasing density of lines for connecting semiconductor devices in integrated circuits leads to congestion in routing, which affects performance and reliability.
Innovation Solution
The integrated circuit design includes standard cells with varying via positions over gate lines for input signals, allowing flexible routing line arrangements and reducing congestion by using gate lines as input pins, thereby increasing the degree of freedom in routing line formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the density of lines for connecting semiconductor devices is increased to improve circuit integration, then the area utilization is improved, but the routing congestion increases
Solution Approach 1:
The patent utilizes the vertical dimension by allowing gate lines to extend into upper metal layers (e.g., M2 layer) to serve as input pins. This dimensional transition enables signals to be routed through multiple layers, effectively adding a vertical routing dimension that reduces horizontal routing congestion while maintaining high area utilization.
Solution Approach 2:
The gate line is given multiple functions: it serves both as the control electrode for the transistor and as an input pin for signal reception. By making the gate line multi-functional, the patent eliminates the need for separate input pin structures, thereby reducing routing congestion without compromising area utilization.
2Device complexity
If standard cells have fixed input pin positions to simplify design, then the design complexity is reduced, but the routing flexibility is limited
Solution Approach 1:
The patent introduces dynamic positioning of input pins by allowing them to be formed at different locations along the gate line (e.g., at different Y-coordinates). This dynamic approach enables the input pin position to be adjusted based on routing requirements, thereby increasing routing flexibility while maintaining relatively simple standard cell designs.
Solution Approach 2:
Different standard cells are configured with input pins at different local positions along their gate lines. This local differentiation allows each standard cell to be optimized for its specific routing context, providing routing flexibility without requiring complete redesign of the standard cell structure.
Data Source
AI summary
An integrated circuit includes plural standard cells performing a same function. The standard cells include a first standard cell and a second standard cell, and the first standard cell and the second standard cell are to the same as each other in terms of an arrangement of internal conductive patterns and are different from each other in terms of a position of a via formed over a gate line through which an input signal is input.