Standard Cell Via Spacing for Routing Interference
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Solution Overview
Problem
In integrated circuit design, routing interference between adjacent pins at different metal layers leads to design rule check violations, particularly with the miniaturization of manufacturing processes, where maintaining the minimum distance between metals becomes challenging.
Innovation Solution
The design employs a standard cell layout with specific via configurations, where the via center-to-via center space is greater than the double of the minimum metal center-to-metal center pitch, and uses two types of standard cells: one with a tip-to-tip space equal to or greater than the DRC space to prevent routing congestion and another with a tip-to-tip space less than the DRC space for non-congested regions, utilizing a placement and routing tool to categorize regions and select appropriate cell libraries for each.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pins are placed adjacent to each other at different metal layers to increase routing density, then routing efficiency is improved, but routing interference occurs causing design rule check violations
Solution Approach 1:
The patent introduces a via layer as an intermediate dimension between metal layers. By placing vias at strategic positions and ensuring sufficient via-to-via spacing, the design enables vertical interconnection while maintaining horizontal separation between adjacent pins on different metal layers, thus preventing routing interference and DRC violations.
Solution Approach 2:
The via structure serves as an intermediary element that connects metal layers vertically while maintaining spatial separation between adjacent pins. The via-to-via spacing requirement acts as a mediating constraint that prevents direct interference between routing paths on adjacent metal layers, allowing high-density pin placement without compromising design rule compliance.
2Area of stationary object
If manufacturing process is miniaturized to reduce device size, then device area is reduced, but maintaining minimum distance between metals becomes difficult
Solution Approach 1:
The patent segments the interconnection structure into distinct vertical (vias) and horizontal (metal) components. By separating the functions of vertical interconnection (via) and horizontal routing (metal) into orthogonal segments, the design maintains clear spatial boundaries between adjacent pins, ensuring that miniaturization does not compromise the minimum distance requirement between metals.
Solution Approach 2:
The patent utilizes the vertical dimension via vias to achieve interconnection, allowing horizontal metal traces to be placed closer together while maintaining sufficient separation through the vertical via spacing. This dimensional separation enables area reduction in the horizontal plane without sacrificing manufacturing precision for metal-to-metal spacing.
3Reliability
If via center-to-via center space is increased to prevent routing interference, then routing congestion is reduced, but cell area increases
Solution Approach 1:
The patent applies local quality by implementing via-to-via spacing requirements specifically at locations where routing interference is most likely to occur between adjacent pins on different metal layers. Rather than uniformly increasing spacing across the entire cell, the design focuses the spacing constraint on critical via regions, thereby preventing routing congestion while minimizing the impact on overall cell area.
Data Source
AI summary
An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.