Standard Cell Wiring Position Adjustment for IC Layout Optimization
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Solution Overview
Problem
As integrated circuits become more complex, the increased real estate occupied by wiring due to limitations in reducing gate lengths of semiconductor devices leads to inefficiencies in layout optimization, necessitating improved methods for wiring optimization to reduce layout area.
Innovation Solution
A computer-implemented method and system for designing and fabricating integrated circuits that adjusts the position of internal wirings within standard cells based on the position of routing wirings, ensuring compliance with design rules by either shifting the internal wiring or replacing cells to maintain minimum distance requirements, thereby optimizing layout and reducing wiring density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate length is reduced to increase device integration, then device density is improved, but wiring real estate increases due to process limitations
Solution Approach 1:
The patent applies dynamics by making the wiring layout adaptive rather than fixed. The system dynamically adjusts wiring positions based on design rules and spatial constraints, allowing the wiring configuration to change in response to different device arrangements and density requirements, thereby optimizing the balance between device integration and wiring space occupation.
Solution Approach 2:
The patent changes parameters by adjusting wiring positions, orientations, and layer assignments based on design rule checks and spatial constraints. The system modifies wiring parameters dynamically to reduce wiring real estate while maintaining functional connectivity, directly addressing the contradiction between device integration and wiring space occupation.
2Area of stationary object
If wiring optimization is performed to reduce layout area, then layout area is reduced, but design complexity increases
Solution Approach 1:
The patent applies preliminary action by performing design rule checks and spatial constraint validations during the placement and routing phase, rather than as a separate post-processing step. This early detection and adjustment of potential violations simplifies the overall design process by preventing complex corrections later, while still achieving wiring optimization to reduce layout area.
Solution Approach 2:
The system implements feedback by continuously checking wiring configurations against design rules and spatial constraints, and automatically adjusting wiring positions and routes based on the check results. This closed-loop approach optimizes layout area while managing design complexity through automated iterative refinement rather than manual complex adjustments.
3Quantity of substance
If internal wiring position is adjusted based on routing wiring position, then wiring density is optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies dimensionality change by utilizing multiple wiring layers to route signals. When spatial constraints or design rules prevent optimal wiring density in a single layer, the system transitions to additional layers, effectively adding a vertical dimension to the wiring layout. This approach optimizes wiring density without excessively increasing position precision requirements within any single layer.
Data Source
AI summary
An integrated circuit including standard cells, a method and a computing system for designing and fabricating the same are provided. A computer-implemented method involves placing, based on a standard cell library, standard cells of an integrated circuit to be fabricated, and routing the placed standard cells. A position of a first wiring of a placed cell among the placed standard cells may be adjusted based on a position of a second wiring used for the routing. The first wiring is provided from at least one standard cell, formed in a same layer as that of the second wiring, and spaced from the second wiring in a first direction. An integrated circuit layout having the adjusted position of the first wiring, is produced.