High-Resistivity Standard Wafer Structure for Epitaxy Calibration
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Solution Overview
Problem
Current standard wafers made from single crystal silicon are limited in providing high resistivity values, making them unsuitable for calibrating high-resistivity epitaxy wafers, and customizing them is costly.
Innovation Solution
A method involving the formation of a reverse epitaxy layer with low resistivity and a target epitaxy layer with high resistivity on a silicon substrate, using four-point probing for resistivity measurement to create a cost-effective standard wafer for calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard wafers are made from single crystal silicon, then manufacturing precision is improved, but resistivity is limited to below 50 ohm/cm and cost increases
Solution Approach 1:
The patent divides the wafer into two distinct layers: a single crystal silicon substrate layer and an epitaxial layer. This segmentation allows each layer to serve different functions - the substrate provides mechanical strength and baseline electrical properties, while the epitaxial layer provides the required high resistivity characteristics, thus achieving high resistivity without the high cost of custom single crystal silicon
Solution Approach 2:
The patent creates a composite structure combining single crystal silicon substrate with epitaxial silicon layer. This composite material approach leverages the advantages of both materials - the structural integrity of single crystal silicon and the high resistivity properties of epitaxial silicon - to achieve performance that neither material could provide alone at reasonable cost
2Measurement precision
If standard wafers are made from single crystal silicon, then measurement precision is improved, but resistivity range is limited
Solution Approach 1:
The patent changes the resistivity parameter by forming an epitaxial layer with controlled doping levels on top of the single crystal substrate. This allows the surface layer to exhibit high resistivity (>50 ohm/cm) while maintaining the structural stability of the single crystal substrate, thereby expanding the measurable resistivity range for calibration purposes
3Measurement precision
If custom single crystal is used to achieve high resistivity, then measurement precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent segments the wafer structure into a standard single crystal substrate (available at normal cost) and an epitaxial layer (formed through controlled deposition). This segmentation enables high resistivity calibration capability without requiring expensive custom-grown single crystal silicon, as the epitaxial layer can be formed on standard substrates
Solution Approach 2:
The patent uses a relatively inexpensive single crystal silicon substrate as the base, which can be mass-produced through standard processes. The high-value calibration functionality is achieved through the added epitaxial layer rather than requiring expensive custom single crystal growth, effectively using a cheaper base material enhanced by a functional layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of a standard wafer with resistivity greater than 50 ohm/cm, enabling precise calibration of high-resistivity epitaxy wafers at a lower cost, improving measurement accuracy and stability.
Implementation Method 1
forming a reverse epitaxy layer overlying the silicon substrate, the reverse epitaxy layer having a second conductive type which is opposite to the first conductive type
Implementation Method 2
measuring a measurement of the resistivity of the target epitaxy layer with four point probing (4PP)
Data Source
AI summary
The present invention provides standard wafers, a method of making the same and a calibration method. The method of making a standard wafer comprise providing a silicon substrate having a first conductive type; forming a reverse epitaxy layer having a second conductive type; forming a target epitaxy layer having the first conductive type; measuring a measurement of a resistivity of the target epitaxy layer with four point probing, the measurement being utilized as a standard resistivity of the standard wafer. In the present invention, the method of making a standard wafer is low-cost and convenient because the standard wafer is made with electrical isolation formed with the reverse epitaxy layer positioned between the silicon substrate and the target epitaxy layer formed after forming the reverse epitaxy layer facilitates in presenting a resistivity of the target epitaxy layer greater than 50 ohm/cm at first and then utilizing the four point probing to measure the resistivity of the target epitaxy layer as the resistivity of the standard wafer.