Standing Semiconductor Test Inserts for Higher Device Density

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Solution Overview

Problem

Existing semiconductor testing systems limit the number of devices that can be tested simultaneously due to the maximized footprint when devices like LPCAMM or DIMM are laid down, which hinders efficient testing throughput.

Innovation Solution

An automated mounting test system that tests semiconductor products in a standing state using a test tray with inserts, a handler, and a tester with socket modules, where the semiconductor products are supported in a standing posture and connected via socket modules for efficient signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor products are mounted in a lying down state with terminals facing the floor, then electrical connection to the test device is achieved, but the footprint occupied by the device is maximized, limiting the number of devices that can be tested at one time

Engineering Contradiction:
Improvenumber of devices tested at one timeVSAvoidfootprint occupied by device
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent changes the mounting orientation from horizontal (lying down) to vertical (standing up), utilizing the vertical dimension to reduce the horizontal footprint. This allows multiple devices to be arranged in a compact configuration within the test device, increasing the number of devices that can be tested simultaneously without expanding the overall footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If semiconductor products are mounted in a lying down state, then electrical connection is simplified, but the test device occupies maximum space, reducing testing throughput

Engineering Contradiction:
Improvetesting throughputVSAvoidspace occupied by test device
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

By transitioning from horizontal to vertical mounting, the patent optimizes space utilization within the test device. The vertical arrangement allows for more efficient use of internal space, enabling higher device density and improved testing throughput without requiring additional space for the test device itself.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If the number of devices tested simultaneously is increased, then testing efficiency improves, but the complexity of the test system increases

Engineering Contradiction:
Improvenumber of devices tested simultaneouslyVSAvoidcomplexity of test system
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the test device into multiple independent socket modules, each capable of testing one or more semiconductor devices. This modular segmentation allows the system to scale capacity by adding identical modules rather than redesigning the entire system, thereby increasing the number of devices tested simultaneously while managing complexity through standardized replication.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The vertical mounting arrangement enables higher device density within each socket module and across the entire test device. This spatial optimization allows more devices to be accommodated in the same footprint, improving productivity without proportionally increasing system complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250264527A1Insert and automated mounting test system for testing semiconductor product in standing state
Publication Date: 2025.08.21 ATECO INC
  • US20250264527A1 patent drawing
  • US20250264527A1 patent drawing
  • US20250264527A1 patent drawing

AI summary

An automated mounting test system for testing a semiconductor product in a standing state according to one embodiment of the present disclosure includes a test tray including a plurality of inserts and having a tray groove into which each insert is inserted, a handler configured to load a semiconductor product to be tested into an empty insert and collect the tested semiconductor product from the insert, a tester including a plurality of socket modules, each facing one of the inserts, in a state where the test tray is seated, and a rack master configured to transport the test tray between the handler and the tester.