Integrated Circuit Star Bus Architecture for Multi-Core Processing

The patent divides the processing system into multiple independent processing cores (first group and second group of processing cores) that can operate simultaneously. Each core handles a portion of the instruction stream, enabling parallel processing. This segmentation allows the system to achieve higher total instruction throughput without requiring a single core to operate at impractically high clock speeds, thereby improving processing capacity without linearly increasing die area for a single high-speed core.

The patent transitions from a single-dimensional sequential processing model to a multi-dimensional parallel processing architecture. By organizing cores into multiple groups that can execute instructions concurrently, the system adds a temporal parallelism dimension. The instruction stream is distributed across multiple cores in different groups, allowing simultaneous execution across multiple processing pipelines, thus achieving higher throughput without proportionally increasing the clock speed of individual cores.

The processing system is segmented into multiple independent core groups that can be independently configured and activated. Each group of processing cores can handle specific instruction streams, allowing the system to scale processing capacity by activating additional groups as needed. This segmentation enables better utilization of processing resources under typical operating conditions by distributing workloads across multiple cores rather than relying on a single overloaded core.

The patent creates a universal processing architecture where multiple groups of processing cores can handle various types of instruction streams. The system is designed to be multi-functional, capable of executing different instruction sets and handling diverse computational tasks across multiple core groups. This universality allows the system to achieve higher theoretical maximum performance by efficiently utilizing all available cores for different types of processing tasks simultaneously.

The memory system is segmented into dedicated random access memories assigned to specific processing core groups. Each group of processing cores has its own dedicated memory resources, allowing simultaneous independent memory access without contention. This segmentation of memory resources ensures that memory access speed is maintained at high levels for each core group while the overall memory capacity is distributed across the die area rather than concentrated in a single large memory block.

The patent implements a hierarchical memory architecture that adds a spatial dimension to memory organization. By distributing dedicated memories across multiple processing core groups rather than using a single centralized memory, the system creates a multi-dimensional memory access structure. This allows parallel memory access operations to occur simultaneously in different core groups, effectively increasing total memory bandwidth without requiring a proportional increase in total memory capacity or die area.

The bus system is segmented into multiple star-bus structures, each serving a specific group of processing cores. Rather than implementing a single complex centralized bus for all cores, the system divides the communication infrastructure into separate star buses for different core groups. Each star bus provides efficient communication within its group, and higher-level buses interconnect the groups. This segmentation reduces the complexity of individual bus structures while maintaining communication efficiency within each segment.

The patent implements a hierarchical bus architecture that adds a vertical dimension to the communication structure. Multiple star buses operate at different hierarchical levels, with lower-level buses serving individual core groups and higher-level buses interconnecting these groups. This multi-dimensional bus hierarchy allows efficient communication within groups at the lower level while providing inter-group communication at higher levels, thereby maintaining overall communication efficiency without requiring a single overly complex centralized bus structure.