Star Topology Memory Routing for Signal Integrity
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Solution Overview
Problem
Current memory device topologies face challenges in maintaining high-speed memory access while preserving command/address signal integrity, particularly in dual in-line memory modules (DIMMs), due to limitations in signal routing complexity and degradation of signal integrity in daisy-chained configurations.
Innovation Solution
The implementation of a star connection topology for memory devices, where clam-shell paired memory devices are coupled to a common command/address signal trace, and additional memory devices are connected to separate traces, ensuring length- and impedance-matched branch portions to minimize signal reflections and maintain signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If daisy-chained configuration is used to connect memory devices, then device complexity is reduced, but signal integrity deteriorates due to signal reflections and degradation
Solution Approach 1:
The patent segments the memory device connections into multiple independent star topologies, each with its own command/address signal trace. This segmentation prevents signal reflections from affecting the entire memory array, as each star topology operates independently with controlled impedance matching at branch points.
Solution Approach 2:
The patent introduces intermediary components including buffer cells, delay cells, and impedance matching networks at branch points to mediate signal transmission. These intermediaries actively compensate for signal degradation and reflections, maintaining signal integrity across multiple memory devices connected in star configuration.
2Productivity
If more memory devices are added to increase memory density, then productivity is improved, but signal integrity deteriorates due to increased routing complexity and signal degradation
Solution Approach 1:
The patent divides the memory array into multiple star topologies, each capable of independently addressing a subset of memory devices. This allows linear scaling of memory density by adding more stars rather than expanding a single daisy chain, maintaining signal integrity through segmentation while increasing overall productivity.
Solution Approach 2:
The patent transitions from one-dimensional daisy-chain topology to two-dimensional star topology arrangement, where memory devices are organized in radial patterns around central branch points. This dimensional change enables more efficient space utilization and signal distribution, accommodating higher memory density without proportional increase in signal degradation.
3Reliability
If star connection topology is implemented with multiple memory devices on separate traces, then signal integrity is improved, but device complexity increases due to additional routing
Solution Approach 1:
The patent merges multiple command/address signal traces into common trunk portions that share impedance-matching characteristics. By combining routing resources and using shared impedance-matching networks at branch points, the patent reduces the overall complexity burden while maintaining the signal integrity benefits of separate trace connections for each memory device.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to memory topologies. An apparatus may include a first plurality of clam-shell paired memory devices arranged in a star connection topology, each clam-shelled pair of the first plurality of memory devices being coupled by a respective matched branch to a first common command address signal trace. The apparatus may include a second plurality of memory devices coupled to a second common command address signal trace.