STAR Semiconductor Structure for NAND Flash Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices with planar type structures face limitations in high integration and performance due to weak channel effects and interference from adjacent cells in NAND flash memory arrays, particularly with vertical channel memory cells connected between single-layer bit lines and word lines.
Innovation Solution
A semiconductor device with a stacked array (STAR) structure featuring vertically stacked semiconductor layers, a gate electrode wrapping around all layers with insulators, and source/drain regions formed on both sides, allowing for single gate, double gate, or gate all around configurations, enabling improved channel control and memory cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar type structure is used for memory cells, then the device structure is simple to manufacture, but the integration density is limited and channel control is weak
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional stacked structure where multiple semiconductor layers are vertically stacked. This dimensional change allows multiple memory cells to be stacked vertically, significantly increasing integration density while maintaining manufacturing feasibility through sequential layer formation processes.
Solution Approach 2:
The memory array is segmented into multiple independent semiconductor layers stacked vertically, with each layer containing memory cells that can be independently controlled. This segmentation allows parallel operation of multiple layers, increasing overall storage capacity and integration density without compromising manufacturing simplicity.
2Device complexity
If vertical channel memory cells are connected between single-layer bit lines and word lines, then the structure is simpler, but the integration density and channel control remain limited
Solution Approach 1:
The patent extends the vertical channel structure to multiple stacked layers, with bit lines and word lines wrapping around or connecting to multiple semiconductor layers. This three-dimensional interconnection architecture enables higher integration density while maintaining relatively simple connection principles compared to fully complex 3D routing.
3Ease of manufacture
If conventional NAND flash memory array structure is used, then the manufacturing process is established, but channel control is weak and adjacent cell interference occurs
Solution Approach 1:
The patent implements different structural configurations for different regions of the memory array. Some cells use gate-all-around structures for superior channel control, while others may use partial gate structures. This local differentiation allows optimization of channel control and adjacent cell isolation in critical regions while maintaining manufacturing efficiency across the entire array.
Solution Approach 2:
The gate structure is nested around the channel in a gate-all-around configuration, with the gate electrode completely surrounding the channel region. This nested structure provides superior electrostatic control of the channel, reducing leakage and improving threshold voltage control, while maintaining compatibility with established manufacturing processes.
4Adaptability or versatility
If planar type memory cells are used, then the device structure is conventional, but high integration is limited
Solution Approach 1:
The patent employs vertical stacking of multiple semiconductor layers to achieve three-dimensional integration, transforming the conventional planar architecture into a stacked configuration. This enables high integration density by utilizing the vertical dimension, while maintaining adaptability to existing manufacturing processes through modular layer formation and standard semiconductor fabrication techniques.
Data Source
AI summary
The present invention relates to a semiconductor device, a memory array and a fabrication method thereof, and more particularly to a semiconductor device having a stacked array structure (referred to as a STAR structure: a STacked ARray structure) applicable to not only a switch device but also a memory device, a NAND flash memory array using the same as a memory device and a fabrication method thereof.