StarNet Neural Network Architecture for 8-Bit Embedded Processing
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Solution Overview
Problem
Existing neural networks are not effectively implemented on low-cost, low-power devices due to the lack of support for floating-point arithmetic, necessitating a need for efficient neural networks using reduced-bit arithmetic and storage, particularly 8-bit arithmetic and storage, which is not adequately addressed by existing frameworks.
Innovation Solution
The StarNet architecture employs reduced-bit processing by modifying the number of bits used for processing and storage, utilizing techniques such as linear quantization, star-shaped filters, and shuffle layers to prevent data overflow, and using non-saturating arithmetic on DSP cores, enabling efficient implementation on devices with 8-bit signed integer support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If 32-bit floating point operations are used for neural network processing, then processing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent changes the bit-length parameter from 32-bit floating point to reduced-bit integer representations (e.g., 8-bit or 16-bit), transforming the neural network operations to match the capabilities of simpler embedded processors while maintaining acceptable precision through quantization techniques
Solution Approach 2:
The patent replaces expensive 32-bit floating point processors with cheaper reduced-bit processors, accepting that the simpler processors have more limited capabilities but are sufficient for the application, thereby reducing device cost and complexity
2Device complexity
If reduced-bit processing is used to simplify device complexity, then device complexity is reduced, but processing precision deteriorates
Solution Approach 1:
The patent applies preliminary quantization to the neural network weights and inputs before processing, pre-scaling the data to appropriate bit representations that prevent overflow during reduced-bit operations while preserving the essential information needed for accurate processing
Solution Approach 2:
The patent incorporates scaling factors and bias terms in advance to cushion against potential overflow conditions, ensuring that intermediate results during neural network processing remain within the limited range of reduced-bit representations
3Device complexity
If reduced-bit storage is used to reduce device complexity, then device complexity is reduced, but working capacity deteriorates
Solution Approach 1:
The patent segments the neural network processing into multiple passes or stages, allowing the system to handle larger effective working capacities by processing data in chunks that fit within the limited reduced-bit storage capacity of embedded devices
Data Source
AI summary
A neural network architecture is used that reduces the processing load of implementing the neural network. This network architecture may thus be used for reduced-bit processing devices. The architecture may limit the number of bits used for processing and reduce processing to prevent data overflow at individual calculations of the neural network. To implement this architecture, the number of bits used to represent inputs at levels of the network may be modified to ensure the number of bits of the output does not overflow the resulting capacity of the reduced-bit processor.