Startup Delay Circuit for Clean Restart After Power Loss
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Solution Overview
Problem
Computer systems or PCs frequently fail to restart after unexpected network interruptions due to residual voltages on the motherboard.
Innovation Solution
Integrate a startup delay circuit into the boot sequence that monitors both mains and system voltages, triggering a delay to discharge residual voltages before restarting, using a detection circuit to identify power failures and a delay timer to ensure a clean boot from 0V.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a startup delay circuit is integrated into the boot sequence to discharge residual voltages, then reliability of restart is improved, but device complexity increases
Solution Approach 1:
The startup delay circuit is activated automatically when a power failure is detected, performing the preliminary action of discharging residual voltages before the boot sequence begins. This ensures the motherboard is fully discharged and ready for a clean startup, preventing restart failures without requiring manual intervention or complex user actions.
Solution Approach 2:
The startup delay circuit acts as an intermediary between the power supply unit and the boot sequence. It monitors the power state, detects failures, and controls the timing of the boot process by introducing a controlled delay period that allows residual voltages to discharge, thereby mediating between the power supply and system startup requirements.
2Productivity
If the delay circuit is activated only when needed, then productivity is improved, but detection complexity increases
Solution Approach 1:
The detection circuit continuously monitors the power supply state and provides feedback to the startup delay circuit. When a power failure is detected (indicated by the power good signal going low), the feedback mechanism triggers the delay circuit to activate. This feedback loop ensures the circuit is activated only when necessary, maintaining high startup efficiency while using simple, reliable detection logic.
Solution Approach 2:
The detection circuit automatically identifies power failure conditions and triggers the delay circuit without requiring external intervention. The system self-monitors its power state and autonomously activates the appropriate startup sequence, eliminating the need for manual detection or complex user input while maintaining efficient operation.
Data Source
Figure 1
Figure 2~3
AI summary
To detect whether a computer system (1) was shut down regularly and/or intentionally, or crashed due to an unexpected power outage, a first monitoring unit (W1) monitors the mains voltage (AC), a second monitoring unit (W2) monitors whether a system voltage (DC) fails, for restarting the computer system (1) after a mains voltage (AC) failure, a start-up delay circuit (ALV) is operated, generating an enable signal (PM_P3V3D_PCH_EN) for restarting the computer system (1). The enable signal (PM_P3V3D_PCH_EN) is set to a low level when the mains voltage signal (PS_PWRGD) is low. When the mains voltage signal (PS_PWRGD) returns to a high level, a delay timer (VT) with a delay time (VZ) is started. Once the delay time (VZ) has expired, the enable signal (PM_P3V3D_PCH_EN) for the startup is set back to the high level.