Startup Gate Discharge Circuit for High-Side FET Turn-On Control
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Solution Overview
Problem
During the initial power up of a power stage, there is often a significant delay before the internal voltage is high enough to discharge the high-side FET gate, leading to partial turn-on of the high-side FET, increased inductor current, and elevated output voltage.
Innovation Solution
A circuit including a current mirror and diodes is used to generate a fast startup signal and a startup discharge signal, which quickly discharge the high-side FET gate before it turns on, thereby preventing excessive current and voltage buildup.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the internal voltage regulator or clamping circuit is used to control the gate driver supply voltage, then the internal voltage is kept within safe limits, but there is a significant delay before the internal voltage rises enough to discharge the high-side FET gate
Solution Approach 1:
The circuit performs preliminary discharge of the high-side FET gate using a dedicated discharge transistor activated during startup. This preliminary action removes the harmful gate charge before the delayed internal voltage rise occurs, preventing unwanted FET turn-on while the voltage regulator is still establishing safe voltage levels.
Solution Approach 2:
A dedicated gate discharge transistor acts as an intermediary component between the gate driver and ground. This intermediary provides a direct discharge path for the FET gate, independent of the slow internal voltage regulator, resolving the contradiction between voltage control safety and discharge speed.
2Power
If the high-side FET gate is not discharged quickly during startup, then the gate driver can operate with sufficient voltage, but the FET partially turns on causing excessive inductor current and output voltage pre-charge
Solution Approach 1:
The circuit applies preliminary anti-action by actively discharging the FET gate before the FET can partially turn on during startup. The discharge transistor removes gate charge in advance, preventing the harmful partial conduction state that would otherwise occur when the gate voltage rises with the internal power rail.
Solution Approach 2:
The circuit converts the potentially harmful situation of delayed gate discharge into a benefit by using the same startup period to establish both the internal voltage rail and to perform the gate discharge. The discharge transistor is activated during the normal voltage establishment phase, turning what would be a harmful delay into a controlled discharge opportunity.
3Speed
If a dedicated fast discharge path is added to the gate driver, then the high-side FET gate can be discharged quickly during startup, but the device complexity increases
Solution Approach 1:
The discharge transistor is merged with the existing gate driver circuitry, sharing the same substrate and control logic. The discharge function is integrated into the gate driver's power management, combining multiple functions (voltage regulation, gate driving, and discharge control) into a single unified circuit block rather than adding a completely separate discharge circuit.
Solution Approach 2:
The gate driver circuit is designed with multi-functionality, where the same control logic and power management structures serve both the voltage regulation function and the discharge control function. The discharge transistor is controlled by the existing startup detection circuitry, making the discharge capability a universal feature of the gate driver rather than a specialized add-on.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively discharges the parasitic capacitor within the high-side power FET before it turns on, preventing excessive current and voltage spikes, and ensuring stable operation of the power stage.
Implementation Method 1
The first diode is connected in series between the second drain and the ground, and the first diode is configured to limit the fast startup signal to a first maximum voltage less than a maximum specified supply voltage
Implementation Method 2
The second diode is connected in series between the fourth source and the ground, and the second diode is configured to limit the startup discharge signal to a second maximum voltage less than the maximum specified supply voltage
Implementation Method 3
The current mirror includes a first FET having a first drain, a first gate, and a first source. The first source is coupled with a supply voltage, and the first gate is coupled to the first drain and to a ground through a resistance element
Data Source
AI summary
A circuit for controlling a discharge transistor for a power stage includes a current mirror, a first diode, and a second diode. The current mirror includes first, second, third and fourth field-effect transistors (FETs) configured to provide a fast startup signal and a startup discharge signal. The startup discharge signal is provided to a gate of the discharge transistor. The first diode is configured to limit the fast startup signal to a first maximum voltage less than the supply voltage, and the second diode is configured to limit the startup discharge signal to a second maximum voltage less than the supply voltage.