Start-Up Reset Circuit Using Phase-Shifted Clocks at Low Vdd
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Solution Overview
Problem
Conventional start-up reset circuits are inefficient and power-hungry, struggling to operate effectively at lower voltage levels due to large chip area requirements and high power consumption, making them unsuitable for modern nanoscale semiconductor processes.
Innovation Solution
A start-up reset circuit utilizing a clock signal generator producing two phase-different clock signals and a flip-flop with adjustable setup time to generate a reset signal, allowing for proper reset operations across varying voltage levels by adjusting the phase difference and setup time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional start-up reset circuit using a comparator and bandgap voltage generator is employed, then the reset signal can be generated, but the chip area and power consumption become excessively large
Solution Approach 1:
The patent extracts and removes the bandgap voltage generator and comparator from the start-up reset circuit, replacing them with a simplified RC timing circuit. This extraction eliminates the large-area components while retaining the essential reset signal generation function through a different mechanism that uses minimal circuit elements.
Solution Approach 2:
The patent employs simple, temporary components (resistors and capacitors) that are inexpensive and occupy minimal space to generate the reset signal. These components serve their purpose during start-up and can be easily integrated without requiring permanent, large-area structures like bandgap generators.
2Reliability
If a conventional start-up reset circuit using a comparator and bandgap voltage generator is employed, then the reset signal can be generated, but the power consumption becomes excessively high
Solution Approach 1:
The patent removes the power-hungry bandgap voltage generator and comparator from the circuit. The replacement RC timing circuit consumes significantly less power because it relies on passive components and simple logic gates rather than active voltage generation and comparison circuits.
Solution Approach 2:
The patent uses low-power passive components (resistors and capacitors) that consume minimal energy during the start-up period. These components generate the necessary timing signal without requiring continuous power supply like the conventional comparator-based circuit.
3Productivity
If semiconductor processes are scaled to nanometer order, then the internal circuit scale becomes smaller, but the voltage source Vdd becomes too low for conventional start-up reset circuits to operate
Solution Approach 1:
The patent changes the operating parameters of the reset circuit by using RC time constants that are appropriate for low-voltage operation. The resistor and capacitor values are selected to generate appropriate timing signals at reduced Vdd levels, making the circuit adaptable to nanoscale semiconductor processes where voltage has been scaled down.
Solution Approach 2:
The patent creates a dynamic timing circuit using RC charging/discharging that automatically adapts to the available voltage level. The circuit adjusts its behavior based on the actual Vdd present, allowing it to function correctly across a range of voltages including the lower voltages required by nanoscale processes.
Data Source
AI summary
A start-up reset circuit includes a flip-flop and a clock signal generator. The clock signal generator generates a first clock signal and a second clock signal, wherein there is a phase difference between the first clock signal and the second clock signal. The flip-flop receives an operation voltage and has a setup time, and further includes an input terminal to receive the first clock signal, a clock input terminal to receive the second clock signal, and an output terminal to output a reset signal, wherein the setup time corresponds to the operation voltage.