Cross-Coupled Starved Inverter Oscillator for Stable Phase Locking
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Solution Overview
Problem
Existing oscillators in semiconductor devices, such as phase lock loop circuits, face challenges in generating stable clock signals due to inefficiencies in inverter designs, leading to suboptimal performance in generating phase-locked clock signals for synchronous DRAM and communication systems.
Innovation Solution
The design incorporates a starved inverter structure with cross-coupled inverters and additional inverter stages, allowing for selective current leakage to and from input nodes, enabling efficient generation of oscillating signals with phase alignment, including quadrature-phase signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inverter designs are used in oscillators, then the device complexity is reduced, but the stability and frequency of oscillating signals deteriorate
Solution Approach 1:
The oscillator is divided into multiple independent inverter stages (first inverter, second inverter, third inverter, fourth inverter) with distinct functions. Each inverter stage processes the signal separately, allowing for better control of oscillation characteristics and improved stability without requiring a monolithic complex structure.
Solution Approach 2:
The inverter structures incorporate dynamic elements such as cross-coupled connections and feedback paths that allow the circuit to adapt its operating characteristics. The starved inverter configuration enables dynamic control of the oscillation frequency and phase, improving signal stability through self-adjustment rather than fixed complex structures.
2Reliability
If starved inverter structure with cross-coupled inverters is used, then the phase-locking capabilities are improved, but the device complexity increases
Solution Approach 1:
The oscillator employs feedback mechanisms where the output of later inverter stages is fed back to earlier stages (e.g., fourth inverter output to first inverter input, second inverter output to third inverter input). This feedback enables phase-locking by continuously adjusting the signal phase to maintain stability, achieving reliable phase-locking without requiring excessively complex external control circuits.
Solution Approach 2:
Multiple inverter stages are merged into a unified oscillation circuit where each inverter serves dual purposes: signal inversion and phase adjustment. The cross-coupled configuration merges the functions of oscillation generation and phase control into a single integrated structure, improving phase-locking capabilities without proportionally increasing overall device complexity.
3Adaptability or versatility
If additional inverter stages are added for quadrature-phase signal generation, then the functionality is improved, but the device complexity and area increase
Solution Approach 1:
The inverter stages are designed to perform multiple functions: the first and second inverters generate in-phase and anti-phase signals, while the third and fourth inverters generate quadrature-phase signals. Each inverter structure serves as a multi-functional building block that contributes to both basic oscillation and advanced phase generation, reducing the need for separate dedicated circuits for each function.
Solution Approach 2:
The oscillator extends from generating simple in-phase/anti-phase signals to generating quadrature-phase signals by adding phase dimensionality. The cross-coupled inverter configuration enables the circuit to operate in multiple phase dimensions simultaneously, providing quadrature-phase output without requiring completely separate oscillation circuits, thus optimizing area utilization.
Data Source
AI summary
One embodiment of the oscillator includes a first starved inverter and a second starved inverter. An inner inverter of the second starved inverter is cross-coupled to an inner inverter of the first starved inverter. The oscillator further includes a first inverter connected to output of the inner inverter of the first starved inverter, and a second inverter connected to output of the inner inverter of the second starved inverter.