State-Change Detection Controller for Real-Time Ethernet Memory
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Solution Overview
Problem
In real-time Ethernet networks, detecting state changes in data stored in a common memory is delayed due to the need to read data from all blocks at predetermined intervals, which can miss timely state changes.
Innovation Solution
A transmitting station with a common memory, a receiver, a state-change information memory, and a state-change detection controller that associates address pointers with state detection words to immediately detect state changes by reading out specific state detection words from the state-change table storage upon receiving data, reducing the need to access all data in the common memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is read from all blocks in the common memory at predetermined intervals, then all transmitting stations can share data periodically, but the detection of state changes is delayed until the next predetermined period
Solution Approach 1:
The patent segments the common memory into multiple blocks, each associated with a specific transmitting station. Instead of reading all blocks uniformly at predetermined intervals, the system selectively reads only the block corresponding to the transmitting station that transmitted the current data. This segmentation enables immediate state change detection for relevant data while maintaining periodic data sharing for other blocks, thus resolving the contradiction between reliable data sharing and timely state change detection.
Solution Approach 2:
The patent applies partial action by reading only the necessary block (excessive action compared to reading all blocks) when data is transmitted. Rather than waiting for the predetermined period to read all blocks in the common memory, the system immediately reads the specific block containing the transmitted data to detect state changes. This partial reading approach eliminates detection delays for critical data while maintaining the periodic reading schedule for other blocks.
2Measurement precision
If all blocks in the common memory are read at each predetermined period, then complete data monitoring is achieved, but the processing load and time consumption increase significantly
Solution Approach 1:
The patent extracts and processes only the relevant block from the common memory when data is transmitted. Instead of reading all blocks at each predetermined period, the system identifies and extracts only the block corresponding to the transmitting station that sent the data. This extraction approach maintains complete monitoring of transmitted data (measurement precision) while significantly reducing processing load and time consumption (productivity) by avoiding unnecessary reads of other blocks.
Solution Approach 2:
The system performs partial reading of only the necessary block when data transmission occurs, rather than reading all blocks. This partial action approach achieves complete monitoring of relevant data changes while improving processing efficiency by minimizing the number of blocks read. The predetermined periodic reading of all blocks is maintained for cases where no specific transmission occurs, balancing monitoring completeness with processing efficiency.
Data Source
AI summary
A transmitting station includes a common memory, a receiver, a state-change information memory, a state-change table storage, and a state-change detection controller. The common memory includes a plurality of blocks storing therein data that is periodically broadcast by scan transmission among other transmitting stations. The state-change detection controller, when receiving the data from the other transmitting station, reads out from the state-change table storage a state detection word of the block corresponding to the other transmitting station of a transmission source of the relevant received data, and detects a state change of a word that is indicated by the common memory address stored in the state-change information memory in association with a target pointer that is an address pointer of the read-out state detection word.


