State-Controlled Peripheral Interface Circuit for Secure Key Isolation

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Solution Overview

Problem

Generic processors face significant demands in handling communications with peripheral circuits, particularly in managing security-related functions and device secrets, necessitating improved interactions and secure manipulation of cryptographic keys.

Innovation Solution

An interface circuit with a register storing a state parameter, capable of controlling access requests and operations based on the state value, intercepts and reroutes data transactions between peripheral circuits, ensuring secure handling of sensitive data and maintaining processor isolation from secrets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the generic processor directly handles communications with peripheral circuits, then the processor can perform cryptographic operations, but the processor becomes overloaded and security is compromised

Engineering Contradiction:
ImprovesecurityVSAvoidprocessor performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces an interface circuit as an intermediary between the generic processor and peripheral circuits. This interface circuit includes a state machine that automatically manages communication protocols and data transfers, allowing the processor to offload communication handling while maintaining security through controlled access to peripheral circuits

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the generic processor manipulates device secrets directly, then cryptographic operations can be performed, but software executed by the processor gains unauthorized access to secrets

Engineering Contradiction:
Improvecryptographic operation capabilityVSAvoidsecret protection
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent segments the system into secure and non-secure domains. The interface circuit contains a state machine that operates in a secure domain, while the generic processor operates in a non-secure domain. This segmentation allows cryptographic operations to be performed by the processor without giving it direct access to secrets, as the interface circuit mediates all interactions with peripheral circuits containing secrets

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interface circuit acts as a mediator that the processor can interact with using standard memory-mapped I/O, while the mediator handles secure communication with peripheral circuits. This allows ease of operation for the processor while maintaining secret protection through the intermediary layer

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If multiple peripheral circuits are connected to the processor, then functionality is enhanced, but communication complexity and processor burden increase

Engineering Contradiction:
Improveperipheral circuit functionalityVSAvoidcommunication management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The interface circuit is designed as a universal intermediary that can manage communications with multiple different types of peripheral circuits through a single standardized interface to the processor. The state machine within the interface circuit adapts to different peripheral protocols, allowing enhanced functionality without increasing processor burden or communication complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4439367B1Circuit and method for interfacing with peripheral circuits
Publication Date: 2025.09.03 STMICROELECTRONICS INT NV
  • EP4439367B1 patent drawingFigure 1
  • EP4439367B1 patent drawingFigure 2
  • EP4439367B1 patent drawingFigure 3~4A

AI summary

This description relates to an interface circuit (112) connected to at least one first and one second peripheral circuit (116, 118, 120, 122), and comprising a register storing a state parameter, the interface circuit being configured to: - receive a request for access for writing or reading, from a processor (104) and to a destination address in the first peripheral circuit; and - generate a write and/or read operation to the first and/or the second peripheral circuit, the operation and its destination being selected according to the state value, the destination address and, for example, a data value from the processor.