Mapping State Elements via Sequential Depth for Equivalence Verification

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Solution Overview

Problem

Conventional equivalence verification methods for digital circuits face challenges such as name alterations during design transformations, difficulty in reverse engineering, and circular problems due to incomplete input information, making them inefficient for mapping state elements across different design levels.

Innovation Solution

The method involves determining sequential depths from primary inputs and outputs to state elements in digital circuits, identifying and mapping state elements with unique sequential depths, and iteratively refining these mappings using feature vectors to ensure accurate equivalence verification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a naming method is used to map state elements, then the mapping process is simple, but the method becomes unusable when names are altered or lost during design transformation

Engineering Contradiction:

Improvesimplicity of mapping processVSAvoidusability when names are altered

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the mapping parameters from element names to structural characteristics (sequential depth, fan-in logic cone structure). This allows the mapping to remain valid even when names are altered during design transformation, as the structural parameters remain invariant across transformation levels.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces structural characteristics as intermediary parameters that mediate between the high-level and low-level designs. These structural features serve as a common language that both design levels can use for mapping, even when direct name correspondence is lost.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If a functional method using canonical representation is used, then the mapping can handle name changes, but it creates a circular problem by requiring all inputs to be mapped

Engineering Contradiction:

Improvehandling of name changesVSAvoidcircular dependency in mapping

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the mapping problem into independent components based on sequential depth levels. By dividing the state elements into distinct depth groups, the mapping can proceed independently for each segment without requiring global knowledge of all inputs, thereby breaking the circular dependency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary classification of state elements by sequential depth before attempting mapping. This preliminary action organizes the elements in a way that eliminates the need for simultaneous mapping of all inputs, allowing the process to proceed systematically from one depth level to the next.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If a simulation method is used to match state elements, then the method can handle design variations, but it becomes difficult to use in the presence of modifications

Engineering Contradiction:

Improvehandling of design variationsVSAvoidusability with modifications

Core Design Contradiction:

Adaptability or versatilityVSEase of operation

Solution Approach 1:

The patent changes from simulation-based matching to structural parameter-based matching. By using invariant structural parameters like sequential depth and fan-in logic cone structure, the method maintains adaptability to design variations while improving ease of operation, as these parameters can be directly extracted without complex simulation.

Inventive Principle:

Principle #35Parameter changes

4Measurement precision

If a structural method performing net-list to net-list comparison is used, then the method examines combinational cone structure, but it has shortfalls in mapping state elements

Engineering Contradiction:

Improveexamination of combinational cone structureVSAvoideffectiveness in state element mapping

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent adds the dimension of sequential depth to the traditional structural comparison method. While conventional structural methods only examine combinational logic, this patent incorporates the temporal dimension of sequential depth, enabling more effective state element mapping by considering both structural and temporal characteristics.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8407639B2Systems and methods for mapping state elements of digital circuits for equivalence verification

Publication Date: 2013.03.26 RAYTHEON CO

AI summary

Systems and methods for mapping state elements of digital circuits for equivalence verification are provided. One method for mapping state elements for equivalence verification between a first circuit and a second circuit includes (a) determining a first sequential depth from primary inputs and primary outputs of the first circuit and the second circuit to each state element thereof, wherein the first sequential depth is a minimum count of state elements along any path between two points of a circuit, (b) identifying and mapping first state elements of the first circuit and the second circuit having a unique first sequential depth, (c) determining a second sequential depth from the identified first state elements of the first circuit and the second circuit to the remaining state elements, (d) identifying second state elements of the first circuit and the second circuit having a unique second sequential depth, and (e) repeating (c) and (d) unless the process is no longer generating new unique mappings of state elements.