State Feedback PLL for Packet Network Clock Recovery

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Solution Overview

Problem

Traditional phase locked loops (PLLs) are inadequate for clock recovery over packet networks due to high levels of jitter and wander caused by packet delay variations, non-stationary noise, and inability to handle multiple timing packet streams, leading to poor performance and reliance on costly stable oscillators.

Innovation Solution

A state feedback controller with an adaptive Kalman filter is used to estimate internal states and generate control signals for a digital controlled oscillator, reducing phase difference and exploiting the diversity of multiple timing packet streams for improved phase tracking and locking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If loop filter bandwidth is lowered to reduce jitter and wander, then wander and jitter elimination is improved, but tracking speed and response time deteriorate

Engineering Contradiction:
Improvejitter and wander eliminationVSAvoidtracking speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The invention segments the control task by introducing a feedforward path that directly processes packet delay variation measurements, separating the high-frequency jitter correction (handled by feedforward) from the low-frequency wander correction (handled by the loop filter), allowing the loop filter to operate at lower bandwidth without sacrificing tracking speed

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces an intermediary feedforward controller that processes packet delay variation measurements and generates corrective signals before they reach the loop filter, effectively pre-filtering high-frequency jitter components and reducing the burden on the loop filter, enabling it to operate at lower bandwidth while maintaining tracking performance

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If traditional PLL is used to handle high levels of jitter and wander, then cost is reduced by avoiding stable oscillators, but performance deteriorates due to inability to remove substantial wander

Engineering Contradiction:
ImprovecostVSAvoidwander removal capability
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The invention enhances the feedback mechanism by directly measuring packet delay variation and using it in a feedforward control path, creating a more effective feedback loop that can remove substantial wander without requiring expensive ultra-stable oscillators, achieving both cost reduction and improved performance

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The invention changes the system parameters by directly measuring and compensating for packet delay variation rather than relying on oscillator stability, transforming the approach from hardware-based stability (expensive oscillators) to software-based compensation (effective algorithm), thereby reducing cost while maintaining wander removal capability

Inventive Principle:
Principle #35Parameter changes

3Speed

If packet filter is used to select minimum delayed timing packets, then initial locking is improved when packets are available, but reliability deteriorates when few or no filtered packets are available

Engineering Contradiction:
Improveinitial locking speedVSAvoidtracking reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The invention makes the system dynamic by adaptively adjusting the feedforward control gain based on the reliability and quality of available timing packets, allowing the system to optimize between aggressive filtering (for fast locking) and conservative processing (for reliability) depending on current network conditions and packet availability

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention enables the system to self-adjust by monitoring packet delay characteristics and automatically adapting its filtering and control parameters, eliminating the need for manual configuration and allowing the system to maintain both fast locking and high reliability across varying network conditions through self-optimization

Inventive Principle:
Principle #25Self-service

4Device complexity

If traditional PLL designed for time-invariant systems is used, then design simplicity is maintained, but performance deteriorates in time-varying packet network environments

Engineering Contradiction:
Improvedesign simplicityVSAvoidphase tracking accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The invention transforms the static traditional PLL into a dynamic adaptive system by incorporating time-varying feedforward control based on real-time packet delay measurements, allowing the system to adapt to changing network conditions while maintaining a relatively simple overall structure through modular addition of the feedforward path

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8599986B2Phase locked loop with optimal state feedback controller
Publication Date: 2013.12.03 MICROSEMI SEMICON
  • US8599986B2 patent drawing
  • US8599986B2 patent drawing
  • US8599986B2 patent drawing

AI summary

In a method of recovering timing information over a packet network at a local receiver, timing information is received at intervals timing from a remote source and compared with a locally generated clock signal to generate an input signal y(k) subject to noise representative of the phase difference between the source clock signal and the local receiver clock signal. The input signal is applied to a state feedback controller, preferably including a Kalman filter, to generate a control signal with reduced noise. The control signal is used to control an oscillator in a way so as to reduce the phase difference and generate a slave clock.