State Storage Latch Clocking for Faster Scan Flop Data Paths
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Solution Overview
Problem
The existing state storage circuitry, such as mux-D scan flops, suffers from slow data signal propagation due to a stack of six gates, which also complicates the clock to output delay, making it difficult to optimize setup time without increasing this delay.
Innovation Solution
The introduction of tristate logic circuitry that is controlled by fixed clock signals, allowing the tristate logic circuitry to operate independently of the scan enable signal, thereby reducing the number of gates involved in data path control and increasing the speed of state storage circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stack of six gates is used in the functional data path, then the data signal can be properly controlled and captured, but the propagation speed of the data signal is reduced
Solution Approach 1:
The patent divides the control of data paths into separate segments: scan data path control and functional data path control. Each path has its own dedicated clock signals (first and second clock signals for scan, third and fourth clock signals for functional). This segmentation allows each path to be optimized independently, resolving the contradiction by enabling fast functional path operation without compromising reliable scan capture.
Solution Approach 2:
The patent extracts the scan enable signal control from the functional data path by introducing dedicated third and fourth clock signals that are held at fixed values during scan mode. This extraction removes the conflicting control logic from the functional path, allowing it to operate at maximum speed while scan operations use the separate first and second clock signals.
2Reliability
If the six gate stack becomes tristated later to permit greater capture time, then the master stage can properly capture the data value, but the clock to output delay increases
Solution Approach 1:
The patent segments the clock control functions by introducing separate first/second clock signals for scan operations and third/fourth clock signals for functional operations. This allows the functional path to use optimized clock timing that minimizes clock to output delay while ensuring reliable capture, without being constrained by scan mode timing requirements.
Solution Approach 2:
The patent changes the clock signal parameters (introducing dedicated third and fourth clock signals with fixed values during scan mode) to optimize the functional data path performance. This parameter change enables independent optimization of capture timing and output delay, resolving the contradiction between reliable capture and minimal delay.
3Adaptability or versatility
If gates switched by the scan enable signal are used to control the functional data path, then scan and functional operations can share the same control mechanism, but the device complexity increases
Solution Approach 1:
The patent segments the clock control into separate signals for scan and functional operations. Instead of using a single scan enable signal to control all gates, dedicated clock signals (third and fourth) are introduced for the functional path that are independently controlled, reducing the complexity of gate control logic while maintaining adaptability for both scan and functional modes.
Solution Approach 2:
The patent creates a universal clock control system where multiple clock signals (first, second, third, fourth) can serve different functions depending on the mode. The third and fourth clock signals serve both scan and functional operations but are optimized for functional path control, reducing overall system complexity while maintaining versatility.
Data Source
AI summary
State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry 2 at its functional input and tristate scan signal insertion circuitry 12 for inserting scan data. The tristate scan signal insertion circuitry 12 is controlled by a first clock signal nclk and a second clock signal bclk. The tristate inverter circuitry 2 is controlled by a third clock signal nfclk and a fourth clock signal flck. The clock generating circuitry holds the third and fourth clock signals at fixed values which tristate the tristate inverter circuitry 2 when in scan mode. This moves scan control logic out of the function path comprising the tristate inverter circuitry into the clock control circuitry.