State Machine Timing Control Against Clock Disturbances
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Solution Overview
Problem
State machines in integrated circuits are prone to malfunction due to disturbances in the clock signal, leading to incorrect output signals and potential data corruption or system crashes, especially at high clock frequencies or when the clock signal is disrupted.
Innovation Solution
A method is implemented to protect state machines by generating an internal clock signal synchronized with the external clock signal, adjusting the duration of evaluation and precharge phases to a minimum duration, and detecting state changes in the slowest signal path to ensure accurate signal propagation and prevent malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to improve processing speed, then productivity increases, but the state machine becomes more susceptible to clock signal disturbances and malfunctions
Solution Approach 1:
An intermediary synchronization mechanism is introduced between the external clock signal and the internal state machine operations. The system uses a synchronization signal that is generated internally and controlled based on the completion of evaluation phases, acting as a mediator that decouples the state machine from direct external clock disturbances while maintaining operational speed.
Solution Approach 2:
The system performs preliminary evaluation of whether the evaluation phase is complete before allowing the next clock cycle to proceed. This preliminary check ensures that all signal propagations are finished before state transitions occur, preventing malfunctions due to premature clock edges even at high frequencies.
2Measurement precision
If the evaluation phase duration is extended to ensure complete signal propagation, then measurement precision improves, but the time for state transitions increases
Solution Approach 1:
The evaluation phase duration is made dynamic rather than fixed. The system continuously monitors signal propagation completion and adjusts the evaluation phase length adaptively - extending it only as long as necessary for complete propagation, then immediately transitioning to the next state. This dynamic adjustment optimizes both accuracy and speed.
Solution Approach 2:
A feedback mechanism is implemented that monitors the completion status of signal propagations during the evaluation phase. Based on this feedback, the system determines when the evaluation is complete and can safely proceed to the next state transition, ensuring accuracy without unnecessary delays.
3Ease of operation
If the clock signal is used directly to trigger state transitions, then ease of operation is maintained, but the system becomes vulnerable to clock signal disturbances and noise
Solution Approach 1:
An intermediary synchronization mechanism is introduced between the external clock signal and the internal state machine operations. The system uses a synchronization signal that is generated internally and controlled based on the completion of evaluation phases, acting as a mediator that decouples the state machine from direct external clock disturbances while maintaining operational speed.
Solution Approach 2:
The system applies preliminary anti-action by checking whether the evaluation phase is complete before allowing the clock signal to trigger a state transition. This preemptive check counteracts the potential harmful effect of clock disturbances by ensuring the system is in a stable state before transitioning, preventing malformed operations.
Data Source
AI summary
A method for protecting a state machine having an operation modeled by a set of states linked to each other by transitions, the state machine evaluating output signals upon each transition during an evaluation phase according to input signals comprising signals evaluated during a previous transition, the method comprising steps of determining a minimum duration of each evaluation phase according to a minimum duration to evaluate the output signals according to the input signals, and of adjusting the duration of each evaluation phase.